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266 Discussions

EPCQL controller I Quartus version 16.0

Chloé_Russell
Beginner
1,241 Views

Hello, 

 

I am trying to access in read and write my EPCQL-1024 from simple soft running in NIOSII. I have the Altera Serial Flash Controller I configured in QUAD mode connected from its avl_csr and avl_mem to the NIOSII. I have tried to access in read and write the EPCQL registers (STATUS, Device ID) and the controller registers FLASH_ISR, or FLASH_IMR, it have been successful. But when I need to erase sector or write to memory. Here lies my problem; I can run nothing on board until power off. When reading the values back from the EPCQL or execute a simple access , it seem to return erroned values. I also tried reading the status register to see if there are processes occurring, but it always reads 0x0. Also when I try to read either the FLASH_ISR, or FLASH_IMR, the EPCQL seems to stop responding and I need to repower the chip then reload my .sof , the read data are correct. I am not sure where to start debugging this and if t's by definition, a flash memory needs a power off after each write operation, then how to write many data at a time to same or different sectors. Any help or points in a direction would be much appreciated.

 

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 Thank you in advance :)

 

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8 Replies
YuanLi_S_Intel
Employee
151 Views
Hi Chloe Russel, Can you check if your write command is using QUAD mode? Also, are you using USB Blaster II to connect your FPGA with Host PC? If it so, can you change the TCK frequency to 6MHz? Regards, YL
Chloé_Russell
Beginner
151 Views
Hi, Thank you for your reply. Unfortunately, I’m using the USB Blaster <https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_usb_blstr.pdf> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_usb_blstr.pdf. I assumed that its frequency is not configurable, although I tried to set it to 6M I’ve got the following messages (I tried some commands, excuse me for being a newbie on this): To answer to your first question, my EPCQ controller is correctly set to the QUAD mode: Best Regards, CR
YuanLi_S_Intel
Employee
151 Views
Hi Chloe, Yes, you are right. USB Blaster doesn't have the ability to change TCK frequency. From your explanation, it seems like the design has no problem as it is able to perform read and write to EPCQ-1024. However, the eclipse get "stuck" after you have performed write operation (erase / write). To recover this, you will need to re-power the board and you are able to see changes on EPCQ-1024. It seems like the connection between Host PC and FPGA is having problem. Can you try with the other cable? Perhaps USB Blaster II with 6MHz TCK Frequency? Regards, YL
Chloé_Russell
Beginner
151 Views
Hi , Thank you for your reply. Can you explain to me please how the connection between Host PC and FPGA could have a problem? Does the frequency of the cable affect the connection between the FPGA and the EPCQL, I have only the USB Blaster I and my controller works at 25Mhz generated by PLL. I do not understand how the frequency cable affects the connection between FPGA and EPCQL following write operations. Best Regards, CR
YuanLi_S_Intel
Employee
151 Views
Hi Chloe, JTAG is the bridge to enable communication between Host PC and FPGA. Correct frequency is needed in order to establish a clean and correct timing waveform for JTAG signals. This is probably the reason that you don’t see any effect after you have performed write operation / erase operation. Once you have re-powered the board, the communication will become normal and you are able to see the action that you have done previously (erase sector or write specific data to specific address). Thank You. Regards, YL
Chloé_Russell
Beginner
151 Views
Hi, I’ve posted a question about FD support, I did not get any reply and I’m confused a little bit using the drivers (I do not know when to use functions with File Descriptor support, does using file descriptor support need to work with Linux?). Your reply will be much appreciated. Here is my question : This is my first use of Software drivers. I'm working with the Quartus standard version 16.0. when I used the "altera_avalon_uart_write" and "altera_avalon_uart_read" functions, things go right.. but when trying to use FD (altera_avalon_uart_write_fd and altera_avalon_uart_read_fd) , the parameter SP points to a false base address although the file has been correctly opened, it returns a valid value (!=NULL). my code is : int main() { altera_avalon_uart_state* sp_UART_0; altera_avalon_uart_state* sp_UART_1; sp_UART_0->base = UART_0_BASE; sp_UART_1->base = UART_1_BASE; char tx_buffer[8] = "BITBANG"; char rx_buffer[8]; alt_fd* fp_uart_1; alt_fd* fp_uart_0; fp_uart_1= open ("/dev/uart_1", O_RDWR); //Open file for reading and writing fp_uart_0= open ("/dev/uart_0",O_RDWR); //Open file for reading and writing printf("call init uart\n"); altera_avalon_uart_init(sp_UART_1, UART_1_IRQ_INTERRUPT_CONTROLLER_ID,UART_1_IRQ); altera_avalon_uart_init(sp_UART_0, UART_0_IRQ_INTERRUPT_CONTROLLER_ID,UART_0_IRQ); int wr = altera_avalon_uart_write_fd (fp_uart_1,tx_buffer,sizeof(tx_buffer)) ; printf("wr = %d\n",wr); alt_busy_sleep(1000000); / delay 1us /// 1 s int rd = altera_avalon_uart_read_fd (fp_uart_0,rx_buffer,sizeof(tx_buffer)) ; alt_busy_sleep(1000000); / delay 1us /// 1 s printf(" rd = %d\n",rd); printf("rx_buffer = '%s'\n\n",rx_buffer); printf("sp_UART_0 base = 0x%08X \n", sp_UART_0->base); printf("sp_UART_0 ctrl = 0x%08X \n", sp_UART_0->ctrl); printf("sp_UART_0 tx_buf = '%s' \n", sp_UART_0->tx_buf); printf("sp_UART_0 rx_buf = '%s' \n\n\n", sp_UART_0->rx_buf); printf("sp_UART_1 base = 0x%08X \n", sp_UART_1->base); printf("sp_UART_1 ctrl = 0x%08X \n", sp_UART_1->ctrl); printf("sp_UART_1 tx_buf = '%s' \n", sp_UART_1->tx_buf); printf("sp_UART_1 rx_buf = '%s' \n\n", sp_UART_1->rx_buf); printf(" rx_buffer = %s\n",rx_buffer); altera_avalon_uart_close (fp_uart_1) ; altera_avalon_uart_close (fp_uart_0) ; free(fp_uart_1); free(fp_uart_0); return 0; } Best regards, CR
Chloé_Russell
Beginner
151 Views
Hi , I’ve generated .jic file of NIOSII system with debug module and my test is successfully running on board. When trying to remove debug module and with same steps (new .hex file to respond new configuration .sopcinfo and new .sof) I’ve generated a new .jic file for the system without debug module and after configuring my board nothing works. Thank you for helping me solving the problem by telling me if I’ve to add some option for the system without debug module. Best regards Chloe
YuanLi_S_Intel
Employee
151 Views
Hi CR, It would be better if you could continue to get support from that thread as it has different issue category with this. The reason is because an appropriate expert will be assigned to your thread. Moreover, we can benefit the community for reference if they have the similar issue. Regards, YL
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