Error: hps_system_AXI_cache_secruity_bridge

[schlee68]

Hi- Everybody

I have received example file in the following site:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/fpga-to-hps-bridges-design-example.html

I have used quartus prime pro 18.1

But compile error message below: 

Error: hps_system_AXI_cache_secruity_bridge.AXI_cache_secruity_bridge: Component AXI_cache_secruity_bridge 1.0 not found or could not be instantiated
Error: qsys-generate failed with exit code 3: 1 Error, 6 Warnings

The "platform designer" has "AXI_cache_security_bridge"

What is the problem?

Thanks!

[JingyangTeh_Altera]

Hi

I am Jingyang and will be the Application Engineer handling your case.

Please give me sometime to retest the project and get back to you as soon as possible.

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi schlee68

Appologies for the late reply.

I manage to generate and compile the design.

Could you try sync the system info by clicking the "Sync System Infos" in the platform designer before generating.

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi schlee68

Any update on this case?

Are you still facing the error after syncing the system info?

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi

Since there are no feedback for this thread, I shall set this thread to close pending. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 10 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.

Regards

Jingyang, Teh