How to program FPGA in Arria 10 HPS?

[sunyeong]

Hello,

I'm reading the below rocketboards document about how to program an FPGA from HPS.

GSRD131ProgrammingFPGA 

According to this document, rbf file is little differnt with Arria10.
It seems that Arria10 has two rbf files instead of having one rbf(soc_system.rbf) file.
(ghrd_10as066n2.periph.rbf , ghrd_10as066n2.core.rbf) 

And it seems that BSP editor also doesn't exists in Quartus Prime Pro 24.1 version.

So, Can you give me proper document releated to Arria10 SoC?
I'm using QSPI boot mode and Arria10 SoC Development Kit now.
And I'm using Quartus Prime Pro 24.1 version.
Thanks.

Regards,
Jung.

[aikeu · Accepted solution]

Hi sunyeong,

You can refer to this document on building the bootloader method using Arria10:

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10

Arria 10 FPGA configuration is done in two steps:

Configuration of periphery(periph.rbf): this allows HPS DDRAM to be brought up, and must do be done in SPL

Configuration of fabric(core.rbf): it configures the actual FPGA core fabric, and can be done from SPL or U-Boot

Thanks.

Regards,

Aik Eu

[sunyeong]

Hello,

Thank you for your comments.

The document you provided was very helpful.

But I have below several questions.

• It seems that the feature you mentioned is similar to Early IO Release feature.
  Is this right?
• It seems that there is some customizing point in SPL for early IO release feature.
  In fit_spl_fpga.its, rbf file is described as "fpga-periph-1", "fpga-core-1" name.
  But in SPL code, rbf file is loaded using specific names("fpga-core", "fpga-periph").
  (first_loading_rbf_to_buffer(), drivers/fpga/socfpga_arria10.c)
  I want to modify some names(fpga-periph-1, fpga-core-1) in fit_spl_fpga.its.
  (fpga-periph-1 -> fpga-periph, fpga-core-1 -> fpga-core)
  Is this the correct way for this feature?
• some functions releated with fpga is not called.
  It seems that spl_fit_load_fpga()(in spl_fit.c) function is not called.
  Is this code not used in Arria 10?

Thank you.

Regards,

Jung.

[aikeu]

Hi sunyeong,

Sorry that I do not understand about the naming of the rbf which you mentioned in your previous statement.

The latest building bootloader for Arria10 will require the periph.rbf for the DDR to work first in order to boot up properly.

The core.rbf will be your FPGA design.

the periph.rbf and the core.rbf can be combined into a single file which is fit_spl_fpga.itb

The below is the QSPI flash memory location to be flashed with different files used as a Golden reference software design(GSRD) for socfpga booting:

"

quartus_hps -c 1 -o pv -a 0x0000000 u-boot-splx4.sfp

(first stage bootloader where DDR will be calibrated with periph.rbf being configured.)

quartus_hps -c 1 -o pv -a 0x0100000 fit_uboot.itb

(second stage bootloader where you will able to enter Uboot user space)

quartus_hps -c 1 -o pv -a 0x0300000 fit_spl_fpga.itb

(consist of the configuration files(periph.rbf + core.rbf) which will be used in booting. Can consider a seperate configuration file which only consist of periph.rbf referring to the #Option 1 in the building bootlolader document)

quartus_hps -c 1 -o pv -a 0x1200000 kernel.itb

(Linux kernel related)

quartus_hps -c 1 -o pv -a 0x2720000 core-image-minimal-arria10-rootfs.jffs2

(Linux kernel related)

"

Can check the repo content for Uboot and Linux kernel in the github link below:

https://github.com/altera-opensource

Thanks.

Regards,

Aik Eu

[sunyeong]

Hi, Aik Eu.

Thanks for your comments.

Okay, I understand that you mentioned.

core.rbf: related to FPGA design

periph.rbf: related to DDR to work first in order to boot up properly.

I previously mentioned that there is an error in u-boot.

The logic of uploading rbf files was skipped because of mismatch configuration name. But error log is not printed.

(u-boot-socfpga/drivers/fpga/socfpga_arria10.c)

static int first_loading_rbf_to_buffer(struct udevice *dev,
				struct fpga_loadfs_info *fpga_loadfs,
				u32 *buffer, size_t *buffer_bsize,
				size_t *buffer_bsize_ori)
{
//...

	for (i = 0; i < count; i++) {
		images_noffset = fit_conf_get_prop_node_index(buffer_p,
							     confs_noffset,
							     FIT_FPGA_PROP, i);
		uname = fit_get_name(buffer_p, images_noffset, NULL);
		if (uname) {
			debug("FPGA: %s\n", uname);

			if (strstr(uname, "fpga-periph") && // "fpga-periph-1" in fit_spl_fpga.its
				(!is_fpgamgr_early_user_mode() ||
				is_fpgamgr_user_mode() ||
				is_periph_program_force())) {
				fpga_node_name = uname;
				printf("FPGA: Start to program ");
				printf("peripheral/full bitstream ...\n");
				break;
			} else if (strstr(uname, "fpga-core") && // "fpga-core-1" in fit_spl_fpga.its
					(is_fpgamgr_early_user_mode() &&
					!is_fpgamgr_user_mode())) {
				fpga_node_name = uname;
				printf("FPGA: Start to program core ");
				printf("bitstream ...\n");
				break;
			}
		}
		schedule();
	}
	
	if (!fpga_node_name) {//foga_node_name is null.
		debug("FPGA: No suitable bitstream was found, count: %d.\n", i);//because of log level, this log is not printed.
		return 1;
	}
//...
}

Don't care about that. 

I am trying to upload rbf files using u-boot command.

This is related to #option1 that you mentioned.

The documentation explains how to upload rbf files using sd card.

But, I can't use sdmmc dauter card, and I am using QSPI boot mode.

So, Is there any way to load rbf files using usb?

Thank you.

Regards,

Jung.

[sunyeong]

Hi, Aik Eu.

I use tftp command for uploading rbf file.

tftp ${loadaddr} fit_spl_fpga.itb
imxtract ${loadaddr} fpga-core ${coreaddr}
fpga load 0 ${coreaddr} ${filesize}

The document that you mentioned said that should upload core.rbf file.

But, in u-boot, uploading core.rbf file is skipped because of below code.

(u-boot-socfpga/drivers/fpga/socfpga_arria10.c)

/* This function is used to load the core bitstream from the OCRAM. */
int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
{
//...
	if (rbfinfo.section == core_section &&
		!(is_fpgamgr_early_user_mode() && !is_fpgamgr_user_mode())) {
		debug("FPGA : Must be in early release mode to program ");
		debug("core bitstream.\n");
		return -EPERM;
	}
//...
}

Which rbf file should I upload? (core.rbf? periph.rbf?)

I tried periph.rbf, it works properly without error log.

Thanks.

Regards,

Jung.

[aikeu]

Hi sunyeong,

The fit_spl_fpga.its referring to Option 2 from the document need to be changed in order to re-generate the fit_spl_fpga.itb file.

I think there is a typo error from your side, you will configure the core.rbf only with the below:

imxtract ${loadaddr} fpga-core-1 ${coreaddr}

Thanks.

Regards,

Aik Eu

[sunyeong]

Hi, Aik Eu.

The fit_spl_fpga.its file is in u-boot code not document file.(https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2024.01/board/altera/arria10-socdk/fit_spl_fpga.its)

The command was not typo error.

In order to use fpga-core configuration name, I used this command.

I think any further conversation is meaningless.

Thank you for support.

Regards,

Jung.

[aikeu]

Hi sunyeong,

Glad to hear that the issue has been resolved.

I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thanks.

Regards,

Aik Eu

[Leo26]

Hello Jung,

It seems like you're working with the Arria 10 SoC and facing some challenges with the FPGA programming and BSP editor. For programming the FPGA in an Arria 10 SoC, you're correct that the process involves two separate RBF files: ghrd_10as066n2.periph.rbf and ghrd_10as066n2.core.rbf, which is different from the single RBF file typically used in other configurations.

Since the BSP editor is not available in Quartus Prime Pro 24.1, you might need to use alternative methods or tools for managing your Board Support Packages (BSP).

For detailed information on programming the Arria 10 SoC and using the QSPI boot mode, I recommend checking the following documents:

1. Arria 10 SoC FPGA Development Kit User Guide - This guide provides comprehensive details on using the development kit, including programming and boot modes.

2. Arria 10 SoC User Guide - This document includes specifics on the FPGA and HPS (Hard Processor System) integration, including the handling of RBF files.

3. Quartus Prime Pro Edition Software User Guide - For understanding the Quartus Prime Pro 24.1 features and limitations, including the absence of the BSP editor.

You can find these documents and additional resources at Ampheo Electronics.

[sunyeong]

Hello, Leo26.

Thank you for comment.

I tried to program rbf files by using programming FPGA from HPS.

But, I still have some problem for using HPS-to-FPGA bridges.

The documents that you mentioned may be helpful to me.

I visit the site you mentioned. But it is hard to find the documents.

I would appreciate it if you could provide a url to that document.

Thank you.

Regards,

Jung.

[Kenny_Tan]

case reopening

[sunyeong]

Hello, Kenny.

My team will use Agilex5 instead of Arria10.

So, I don't need the answer about this issue. 

I appreciate your supports.

Regards,

Jung.