Hwlib example preloader questions

CAlex · ‎05-12-2023

Hi,

I'm working on the cyclone V soc HWLIB example from rocketboards.org

Hardware Library (HWLibs) | Documentation | RocketBoards.org.

I built the u-boot-socfpga on my another laptop with

ubunut 22.04LTS

u-bootloader-socfpga newest(2022.07)

and copied to my working laptop :

Win 11

SOCEDS 20.1,

Quartus Prime Lite 22.1

ARM DS 22.2

The service connected to the board successfully.

Then it had the following error:

/*--------------------------------------------------------------------*/

Connected to stopped target Intel SoC FPGA - Cyclone V SoC (Dual Core)
cd "D:\board\cyclone_V_soc\ARM DS\workspace21.1"
Working directory "D:\board\cyclone_V_soc\ARM DS\workspace21.1"
Execution stopped in SVC mode at S:0xFFFF0000
S:0xFFFF0000 B {pc}+0x84 ; 0xffff0084
set substitute-path "/home/chun/cv_GHRD/cv_soc_devkit_ghrd/software/bootloader/u-boot-socfpga/arch/arm/include/asm/arch/" "D:\board\cv_soc_devkit_ghrd\software\bootloader\u-boot-socfpga\arch\arm\mach-socfpga\include\mach\"
source /v "C:\Program Files\Arm\Development Studio 2021.1\sw\debugger\configdb\Scripts\altera_target_check.py"

No SYSID registers could be found. Has a peripheral description file been supplied?

source /v "D:\board\cv_soc_devkit_ghrd\software\bootloader\debug-spl.ds"
+stop
WARNING(CMD315): Target is not running
+wait 5s
+reset
+stop
WARNING(CMD315): Target is not running
+wait 5s
+set trust-ro-sections-for-opcodes off
+loadfile $sdir/u-boot-socfpga/spl/u-boot-spl 0x0
Loaded section .text: S:0xFFFF0000 ~ S:0xFFFF962D (size 0x962E)
Loaded section .rodata: S:0xFFFF9630 ~ S:0xFFFFB28C (size 0x1C5D)
Loaded section .data: S:0xFFFFB290 ~ S:0xFFFFB337 (size 0xA8)
Loaded section __u_boot_list: S:0xFFFFB338 ~ S:0xFFFFB983 (size 0x64C)
Entry point S:0xFFFF0000
Target has been reset
Execution stopped in SVC mode due to a breakpoint or watchpoint: S:0x00000000
S:0x00000000 LDR pc,[pc,#24] ; [0x20] = 0xA8
+start
Reloading program
Starting target with image D:\board\cv_soc_devkit_ghrd\software\bootloader\u-boot-socfpga\spl\u-boot-spl
Running from entry point
WARNING(CMD399-COR168):
# in D:\board\cv_soc_devkit_ghrd\software\bootloader\debug-spl.ds:8 while executing: start
! Failed to start the target
! No function named "main" could be found
WARNING(CMD407): Trying the entry point instead
Execution stopped in SVC mode at S:0xFFFF0000
In boot0.h
S:0xFFFF0000 10,0 ARM_VECTORS
+wait
+restore $sdir/u-boot-socfpga/spl/u-boot-spl.dtb binary &__bss_end
ERROR(ITR14-EXP17):
# in D:\board\cv_soc_devkit_ghrd\software\bootloader\debug-spl.ds:10 while executing: restore $sdir/u-boot-socfpga/spl/u-boot-spl.dtb binary &__bss_end
! "&__bss_end" is not a valid address
! Cannot take the address of the object
ERROR(CMD656): The script D:\board\cv_soc_devkit_ghrd\software\bootloader\debug-spl.ds failed to complete due to an error during execution of the script
quit

/*---------------------------------------------------------------------------------------------------------*/

The ds file is the same file as the hwlib showed:

/*-----------------------------------------------------*/

stop
wait 5s
reset
stop
wait 5s
set trust-ro-sections-for-opcodes off
loadfile $sdir/u-boot-socfpga/spl/u-boot-spl 0x0
start
wait
restore $sdir/u-boot-socfpga/spl/u-boot-spl.dtb binary &__bss_end

// this is where the mistake happens. If I changed the &__bss_end to 0xffff0000(start point of the ocr) then it cant stop at

// spl_boot_device (basically ran over 60s and shut down)
tbreak spl_boot_device
continue
wait 60s

/*-----------------------------------------------------*/

I cant find out any solutions yet

Could you guys help me with that?

If you succeed in your windows environment, do please share your software file please.

Reguards.

CAlex · ‎05-12-2023

Update 2023/5/12

I've tried the branch origan/2020.04

with make socfpga_cyclone5_defconfig

and it worked.

if it is after 2021 the preloader will showed up the error mentioned.

you guys can try 2022 branch with higher version of ARM DS.

Or there is some settings on newer version u-boot you must set i guess.

CAlex · ‎05-12-2023

Update 2023/5/12 v2

Now I'm doing two tests

1. Run Example FPGA using GCC with error:

process_begin: CreateProcess(NULL, cp C:\intelFPGA\20.1\embedded/ip/altera/hps/altera_hps/hwlib ., ...) failed.

Maybe the reason is no permission to copy from C:\

Or duel to some environment issue.

I started the ARMDS with SOCEDS in WSL2 Ubuntu 18.04 LTS , but it still saied it cant find SOCEDS_DEST_ROOT. So I pointed the SOCEDS_DEST_ROOT to SOCEDS_ROOTDIR.

2. Run Example FPGA using ARMCC with error:

D:\board\cyclone_V_soc\intel-socfpga-hwlib\tools\newlib\usr\arm-eabi/include\sys/_types.h:167:5: error: unknown type name 'wint_t'
wint_t __wch;
^
1 error generated.

I ran it with Armclang (arm compiler 6) since I didnt have the access on 5 with a little changes on makefile. All went well except for this error.

Do you guys have any solutions?

CAlex · ‎05-12-2023

Update 2023/5/12 v3

While doing example of cp .sof, there is no cycloneV GHRD under SOCEDS /hardware file. Only A10 GHRD ones.

For real, have you ever planned to update the SOC?

Jeet14 · ‎05-16-2023

Hi,

I will be working on this forum case.

Let me check on this internally and will come back ASAP.

Regards

Tiwari

Jeet14 · ‎05-18-2023

Hi,

For creating and compiling preloader for cyclone V, you need to still use the bsp_editor. Handoff mechansim got changed for cyclone V, arria 10 from v20.3 onwards. you can refer below link

https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10

Let me know if you have any other query on this.

Regards

Tiwari

Jeet14 · ‎05-21-2023

Hi,

Let me know if you have any query on this.

Regards

Tiwari