Intel® Stratix® 10 L- and H-Tile Transceiver PHYの使い方について

[xzeng14]

①Stratix10で搭載されるPCIe PhyのPower-Onリセットに関する質問です。リセットシーケンスの中、Phyのrx_is_lockedtodata信号が立ち上がる条件として、rxが対向Phyからトグルした信号を受信したことだと見受けられます。この認識は正しいでしょうか？

②上記質問の回答がYesの場合の追加質問になります。　

Stratix10のPCIe Phyのリセットの完了させるには、localよりもHost側のPhyが先にリセットを完了し、localへデータを送信しないといけません。Stratix10 PCIe Phy同士を繋いで使用する場合、localとhostがお互いに対して何かのデータを送信し合う仕組みが必要だと考えています。この認識は正しいでしょうか？

※simulation上、そうしないとlocalもhostも対向からデータを受信できず、rx_is_lockedtodata信号が立ち上がらない状態になりました。

[CheePin_C_Intel]

Hi,

Thanks for your update. Sorry for the inconvenience. If you dont mind, would you mind to help further elaborate your inquiries in English just to avoid I misunderstanding your specific inquiries. Please let me know if there is any concern. thank you very much.

[xzeng14]

Hi

The following is the description in English.

Q1. It is a question about the power-on sequence of PCIe Phy in Stratix10.

According to the user manual, I think that to assert signal "rx_is_lockedtodata", it's necessary to receive some toggled signal from link partner by rx_serial_data. Otherwise, the reset would not end and signal "phystatus" would not be de-asserted. Is my understanding correct?

Q2. It is an additional question in case that answer to Q1 is yes.

To finish the reset of PCIe phy, the Phy in Host-side must finish its reset before Local-side does, otherwise the Host-side can not transmit toggled signal to Local side. In case that I connect 2 stratix10 PCIe phys as Local and Host, I think I should consider a method to transmit data to each other within their reset period. Is that correct?

P.S. In my simulation, if I don't do this, signal "rx_is_lockedtodata" can not be asserted and "rx_digitalreset" never end as both side can not receive toggled signal from their link-partner.

Best regards

[CheePin_C_Intel]

Hi,

Thank you very much for your help in the translation.

Please see my responses as following:

Q1. According to the user manual, I think that to assert signal "rx_is_lockedtodata", it's necessary to receive some toggled signal from link partner by rx_serial_data. Otherwise, the reset would not end and signal "phystatus" would not be de-asserted. Is my understanding correct?

[CP] Yes, your understanding is correct. The RX need to received toggling data from link partner before the CDR can achieve lock-to-data and assert rx_is_lockedtodata.

Q2. To finish the reset of PCIe phy, the Phy in Host-side must finish its reset before Local-side does, otherwise the Host-side can not transmit toggled signal to Local side. In case that I connect 2 stratix10 PCIe phys as Local and Host, I think I should consider a method to transmit data to each other within their reset period. Is that correct?

[CP] Yes, your understand is corret. You would need to send some toggling signal to Local before it can achieve CDR lock-to-data. Else, it will continue to wait and rx_digitalreset will remain asserted.

Please feel free to let me know if you would like to further engage our PCIe expert to provide further guidance on the PCIe link up. If yes, you may help to create a new Forum case and let me know the number so that I can help to route. I am unable to duplicate case from this probably due to access limitation.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[xzeng14]

Hi

I submitted ticket #04663816 just now. Could you please route it to your PCIe expert team?

Best regards.

[CheePin_C_Intel]

Hi,

Thanks for your help. I have notified the PCIe team for routing yesterday.

Thank you.

[xzeng14]

Hi,

Thank you for your support!

And please let us know the answer ASAP as it is urgent.

Please feel free to firstly answer part of the questions if it takes time

to check all of them.

Best regards.