Is it possible to reach nearby CLBs optimally fast while using openCL?

[DTóth]

Hi,

I am working on a research project to deepen my knowledge in parallell computing, and I have just scratched the surface of FPGA technology.

To the best of my knowledge opencl is compatible with FPGAs. I would like to have my openCL kernels reach information locally which is stored in other CLBs nearby. The problem with this is I don't see any possibility to do that iteratively.

Correct me if I'm wrong but the only option openCL gives to reaching local kernel-related information is through the local memory space. The only problem with that is that local memory access is restricted to user defined local workgroups. Local workgroups can be defined in such a way that the user is able to define sections in the board, whom have a common memory allocation space.

That kind of logic would not fit the purpose of my project, however in FPGA architecture there is such a thing as local addressing ( neighbouring CLBs, rows and lines ). A CLB is able to have input from a nearby CLB through the addressing system optimally, becuase the device is wired in a way which makes this possible. Is there any way openCL is able to use this capability of FPGAs?

Thank you for any help in advance!

[MuhammadAr_U_Intel]

Hi,

If I understand you correctly, you are trying to read directly from CLB.

Let me explain how logic is implemented in FPGA.

In FPGA user logic written in (HDL language like verilog/ VHDL) or even OpenCL kernel code get implemented in CLB by Quartus. Having said that Quartus will go through Synthesis followed by Fitter stage to populate logic in CLB's. So its a netlist that is implemented in CLB's, Fitter optimizes the location to achieve performance.

I don't think you will be able to read from CLB it self, best you can do is open Chip Planner and see how logic is implemented.

Hope this helps.

Thanks,

Arslan