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Hi, I was wondering if there are any specific memory tests that can be run on the Arria 10 FPGA. I am using an EMIF IP to connect to the external DDR component and want to make sure if all the parameters in the EMIF IP are right and I am able to access the DDR. I did find the following link
But it says its for stratix and cyclone devices. Any Suggestions?
Regards,
Karthik
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Hi Karthik,
The link provided is not related to DDR. I suggest you to generate the synthesis example design which contain a traffic generator to test the memory and signal an overall pass or fail status of your DDR.
You can refer to “Chapter 13: Functional Description—Example Designs” of this EMIF handbook for more details on how to generate the example design and how the traffic generator works.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_ip.pdf
I sincerely hope this helps.
Thanks
Regards,
NAli1
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