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Problems about PCIe Link-Up of Stratix10




I have a reset problems when combining the PLDA controller with Stratix10 PCIe Phy. Could you please check the following question?


Q1. I am using Stratix® 10 L- and H-Tile Transceiver PHY as a PCIe Phy. However, I found that this Phy needs to receive toggled serial signal from link-partner to finish its reset, which is different from the PIPE spec. And when I used an "PLDA controller + Stratix10 Phy" combination as both local and host, the reset of Phy never end as the controller won't transmit anything within reset period.

So my question is, does this Phy have ever worked successfully with controllers except for the Stratix10 PCIe controller?(i.e., Synopsys, Cadence, PLDA)


Q2. Actually, I am trying to combine PLDA controller and Stratix10 Phy. And I stucked at the problem I mention at Q1. Do you know any work around about it?


Q3. Is there any other problem I would probably have besides the reset issue? If there is, please let me know the work around for that too.


Q4. In reset and detect phase, what parallel data should I transmit to the link-partner? I tried to transmit the following data to the link-partner but the link-partner got a 8b10b encode/decode error(rxstatus=2'd4).

16'd1111 -> 16'd2222 -> 16'd3333 -> 16'd4444 -> 16'd5555 -> 16'd1111 -> ...


Best regards

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2 Replies

Hi ,

Let me internally any one is used PLDA controller + S10 Tile . Kindly give me some to get back to you

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As of now, we do not have official reference design and use case for the above

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