Questions about mSGDMA

[Anpeng]

Hi, all!

I'm currently learning how to implement data transfer using mSGDMA and have created a Qsys project for simulation verification. However, the simulation results show that the mSGDMA isn't functioning properly, and I need some assistance.

Below is my system view (with mSGDMA mode set to MM->MM):

During simulation, I performed the following steps:

1. Wrote data to address 0 of mem_s1 (32-bit data width), corresponding to the Avalon-MM address 20'b0.

2. Configured the mSGDMA descriptor with: Read address: 20'b0. Write address: 20'hF0000 (address 0 of mem_s2) .Transfer length: 4 bytes.

However, the data transfer did not occur. Below are the simulation results:

Anpeng

[JingyangTeh_Altera]

Hi

Is it possible if you could share me your project and the steps of running the simulation.

So that I could reproduce it on my end.

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi

Do you have a follow up on this case?

Regards

Jingyang, Teh

[whitepau_altera]

Hello Anpeng, thanks for posting.

In Chapter 31 of the Embedded Peripherals IP User Guide, there is a section that mentions that you need to commit the descriptor information using the 'go' bit in the control field (bit 127). 
31.4.6. Control Field

In your modelsim screenshot, I can see that bit 127 is clear, can you try setting it?

[JingyangTeh_Altera]

Hi

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh