Reconfigure FPGA Agilex 7 M-series without recompile Yocto Linux

[ihsan28]

Hi,

We have Agilex 7 M-series. We managed to run an example of Yocto Linux on the ARM core, and based on my understanding, every time we have a new bitstream, we need to compile Yocto again and rewrite the SD card. right?

So, I guess there is no Ubuntu support or ready for ARM core in Agilex 7, like in Xilinx Zynq, they have Ubuntu support. But in our FPGA, we want to find a way to reconfigure the FPGA fabric without re-burning the SD card. Is it in any way possible to do that?

I noticed about configure via AVSTx8. But I am still confused about that and still doubt if that's what I need or not, because it says after reboot, it will be stuck, so there is no reboot for the ARM core.

Please help me with a hint or info regarding that. Thank you very much.

Best regards,
Ihsan 

[RolandoS_Altera]

Hello Ihsan

If you have changes in your hardware design and don't want to run again Yocto, to create the SD Card image with the .core.rbf inside, there are a couple of options:

1) You can Update the kernel.itb (with the new .core.rbf) manually and then update manually the SD Card image following the instructions in:

• https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/m-series/hbm2e/ug-gsrd-agx7m-hbm2e/#how-to-manually-update-the-kernelitb-file
• https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/m-series/hbm2e/ug-gsrd-agx7m-hbm2e/#how-to-manually-update-the-content-of-the-sd-card-image

    Note that the kernel.itb is created with several components as described in https://www.rocketboards.org/foswiki/Documentation/SingleImageBoot#A_42Linux_DTB_patch_with_location_of_SPT0_42

2) You can load the new .core.rbf into SDRAM from U-Boot using TFTP (you need to set up a TFTP Server in your development machine) and perform the FPGA configuration also from U-Boot and then launch Linux following the next steps:

  # setenv autoload no
  # dhcp
  # setenv serverip <your development machine IP>
  # tftp ${loadaddr} <your .core.rbf> 
  # dcache flush
  # fpga load 0 ${loadaddr} ${filesize}
  # bridge enable
  # setenv bootargs "early panic=-1 root=${mmcroot} rw rootwait";
  # fatload mmc 0:1 ${loadaddr} kernel.itb
  # bootm ${loadaddr}#board-0;

In this 2nd option you boot to Linux using board0 configuration which let U-boot know that it doesn't need to perform FPGA configuration because it was already done (if you use board-4 configuration, bootm will perform the FPGA configuration again using the .core.rbf inside the kernel.itb which will be the old core.rfb).

The .core.rbf that you configure corresponds to the 2nd phase of the fabric design. The new 1st phase still need be included in the HPS rbf as indicated next:

https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/m-series/hbm2e/ug-gsrd-agx7m-hbm2e/#create-bootable-hps-rbf-file

Thanks

Rolando

[khtan]

Hi Ihsan,

Is there any further question related to this topic, otherwise I would like to set this thread to community support.

Thanks

Regards

Kian

[khtan]

Hi Ihsan

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thanks

Regards

Kian