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Relaying network packets from the HPS to the FPGA and vice versa on Cyclone V


I am looking for design guidance in using the FPGA-to-HPS and HPS-to-FPGA bridges on a Cyclone V SoC FPGA. I am using the DE10-Standard board, which only has a Ethernet port connected to the HPS. I would like to relay the network packets to the FPGA for processing. What would be the best way to achieve that?

I have read about the F2H and H2S bridges. Also the lightweight bridge, but which I suppose would be less appropriate for transferring packets since the lower throughput. But there is also the SDRAM, which seems to be another way to transfer data between the HPS and the FPGA. What would be more appropriate between the bridges and the SDRAM for transferring packets?

On the HPS side, I was thinking about using DMA (I think mSGDMA) to reduce processor usage while transferring to the FPGA. Same could be done for the EMAC. Right now I am running Linux on the HPS, so I am not sure how to interface DMA.

On the FPGA side, I would like to be able to use a streaming interface, like Avalon-ST to receive and send packets. Does Intel have such a wrapper since the bridges uses AXI?

Thank you in advance for your time.

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