SD Card Boot

[malcolm_locke]

Hi,

I have an Agilex 5 Modular Development Board which I can boot with the supplied SD Card.

I have tried to update to the latest image at Index of /2025.04/gsrd/agilex5_mk_a5e065bb32aes1_gsrd/,

However, after programming an SD Card with this image, as far as I can tell, my board doesn't boot. I get no output from the serial port so I don't have any way of debugging.

Please can you help with any advice how to proceed to diagnose what is going wrong?

Many thanks

Malcolm

[Jeet14]

Hi Malcolm,

I hope you have reprogrammed the new .jic image to QSPI before using the sd card image.

This .jic image is given on the same link-https://releases.rocketboards.org/2025.04/gsrd/agilex5_mk_a5e065bb32aes1_gsrd/

Please confirm.

Regards

Tiwari

[malcolm_locke]

Hi Tiwari,

Many thanks for your answer. After programming the QSPI with the image you suggested, I was able to boot linux successfully ( I believe from the SD Card!).

Please can you give a brief explanation as to why this was necessary? What was preventing linux from booting?

Many thanks

Malcolm

[JingyangTeh_Altera]

Hi Malcolm

This could be due to the mismatch in the hardware design.

For the the Hardware Design in the GSRD, it is HPS first configuration.

It is separated into initial configuration for the HPS and the core configuration of the FPGA.

The initial configuration is stored in the QSPI Image and the second configuration is in the SDCard.

For a normal boot, both configurations must be of the same build.

That could be the possible problem you are facing. I could not determine that without looking at the error from the bootlog.

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi

Do you have any follow up question on this?

Regards

Jingyang, Teh

[malcolm_locke]

Hi Jingyang,

Thanks, I think that makes some sense but I will have to re-read the information about how the configuration scheme works - it is not like the Cyclone V SoC that I am used to!

When you mentioned looking at the bootlog, how can I do this if I don't get anything out on the serial port?

Thanks

Malcolm

[SueC_Altera]

Malcolm -  Our architecture has changed quite a bit since Cyclone V! You may find the HPS Booting UG to be helpful.

Sue

[JingyangTeh_Altera]

Hi Malcom

In that case, if you do not get any serial output.

It is best to verify the boot binaries are generated properly or the boot related switches are toggled correctly.

If that does not work, we will need to debug it using the debugger.

Also as suggested in the previous comment, going through the boot user guide will be helpful too.

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh

[BrianSune_Froum]

@JingyangTeh_Altera 

I encountered the issue for 2025 and i switched to 2024.07 to confirm all basic function sanity.

Now i am switching back to settle the 2025.01 or 2025.04 issue on the boot for Cyclone V.

Same situation that after the message:

"

U-Boot SPL 2025.01-gcd3a9044d661-dirty (Sep 01 2025 - 08:57:07 +0800)
Trying to boot from MMC1

"

I had study short on that document and if not wrongly understand.

The A2 partition is no longer use?

The U-Boot is a must to use Jtag or QSPI or Flash based chip to store the 1st boot data?

It is possible to change to A2 partition like 2024.07?

Thank you

[KennyTan_Altera]

case reopening

[BrianSune_Froum]

@KennyTan_Altera 

Thank you for op this ticket again.

@JingyangTeh_Altera 

Under investigation we found that the das-uboot 2023 had no issue while latest 2025 not even pass the spl LD compile.

Meanwhile, the A2 settings and partition for RAW is same between u-boot-socfpga 2024 and das-uboot 2023.

With on the above info altera u-boot-socfpga 2025 aligned with the latest 2025 das u-boot.

However, only u-boot-socfpga 2025 able to compiled w/o issue but unable to load the RAW partition properlly.

Please help or guide what  settings are correct.

[BrianSune_Froum]

@KennyTan_Altera 

Issue solved. The U-Boot 2025 .01 or 0.4 both changed and the configurations are no longer work from default defconfig.

The boot now can work .

[SueC_Altera]

Thanks for posting your solution, Brian.

Just for clarity - are you saying the 2025 Uboot works or no?

Thanks,

Sue

[BrianSune_Froum]

@SueC_Altera 

All user got to change the "socfpga_cyclone5_defconfig" in order of only MMC/SD card Boot normally.

Both 2025.01 and 2025.04 after modification will work but you got to know how to set the SPL settings.

[SueC_Altera]

Thank you Brian.  I'll ask the team to make that clearer in the documentation.

Sue

[RolandoS_Altera]

Hello Brian,

I am in charge of updating the build instructions related to Agilex 5 and we want to improve these as much as we can. Could you please provide more details of the configuration that you needed to do to boot successfully?

Were you using the instructions provided in https://altera-fpga.github.io/rel-25.1.1/embedded-designs/agilex-5/e-series/premium/boot-examples/ug-linux-boot-agx5e-premium/ to build your SPL for the modular dev-kit?

You mentioned that you needed to change socfpga_cyclone5_defconfig, may I know why you started with this defconfing instead of the  one specific for Agilex 5 ( socfpga_agilex5_defconfig )?  

Thanks in advance

Rolando

[malcolm_locke]

Hi Rolando, I am pleased to hear that you are updating the build instructions for Agilex 5! I have been trying to follow the instructions in this link

https://altera-fpga.github.io/rel-25.1.1/embedded-designs/agilex-5/e-series/modular/boot-examples/ug-linux-boot-agx5e-modular

for the Boot from QSPI but have given up as, having got around a number of errors, I managed to create and program my QSPI, only for to fail to boot (I can't even open the Serial Port), at which point I have no way to debug what is happening...

One error that I have relates to bl31.bin which i built successfully in the Boot from SD Card stage, but when I run bitbake in the QSPI stage, i get this error:

DEBUG: Executing shell function do_compile cp: cannot stat '/home/malc/agilex5_top/yocto/build/tmp/deploy/images/agilex5_dk_a5e065bb32aes1/bl31.bin': No such file or directory WARNING: /home/malc/agilex5_top/yocto/build/tmp/work/agilex5_dk_a5e065bb32aes1-poky-linux/u-boot-socfpga/v2025.04+git/temp/run.do_compile.19724:163 exit 1 from 'cp /home/malc/agilex5_top/yocto/build/tmp/deploy/images/agilex5_dk_a5e065bb32aes1/${file} /home/malc/agilex5_top/yocto/build/tmp/work/agilex5_dk_a5e065bb32aes1-poky-linux/u-boot-socfpga/v2025.04+git/build/${config}/${file}' WARNING: Backtrace (BB generated script): #1: do_compile, /home/malc/agilex5_top/yocto/build/tmp/work/agilex5_dk_a5e065bb32aes1-poky-linux/u-boot-socfpga/v2025.04+git/temp/run.do_compile.19724, line 163 #2: main, /home/malc/agilex5_top/yocto/build/tmp/work/agilex5_dk_a5e065bb32aes1-poky-linux/u-boot-socfpga/v2025.04+git/temp/run.do_compile.19724, line 301

PS. I am using WSL2.

In the boot from QSPI section, it is unclear what, if anything I need to do with the SD Card...

Also, on this page:

HPS GSRD User Guide - Altera FPGA Developer Site

The 2 links below don't work.

Prebuilt Binaries¶

The Agilex 5 Modular Development Kit GSRD binaries are located at https://releases.rocketboards.org/2025.08/:

Boot Source Link

SD Card	https://releases.rocketboards.org/2025.08/gsrd/agilex5_modular_gsrd/
QSPI	https://releases.rocketboards.org/2025.08/qspi/agilex5_modular_qspi/

and, in this section the link to rocketboards doesn't work.

Booting from QSPI¶

---

This section presents how to boot from QSPI. One notable aspect is that you need to wipe the SD card partitioning information, as otherwise U-Boot SPL could find a valid SD card image, and try to boot from that first.

Wipe SD Card

Either write 1MB of zeroes at the beginning of the SD card, or remove the SD card from the HPS Daughter Card. You can use dd on Linux, or Win32DiskImager on Windows to achieve this.

Write QSPI Flash

1. Power down board

2. Set MSEL dipswitch S4 on SOM to JTAG: OFF-OFF

3. Power up the board

4. Download and extract the JIC image, then write it to QSPI:

wget https://releases.rocketboards.org/2025.08/qspi/agilex5_mk_a5e065bb32aes1_qspi/agilex_flash_image.hps.jic.tar.gz
tar xf agilex_flash_image.hps.jic.tar.gz
jtagconfig --setparam 1 JtagClock 16M
quartus_pgm -c 1 -m jtag -o "pvi;agilex_flash_image.hps.jic"

If you can sort out these issues that would be a great help...

Thanks

Malcolm

[RolandoS_Altera]

Hi Malcom

I confirmed that the links in the Agilex 5 GSRD pages pointing to the binaries is incorrect, the correct paths are the following:

Agilex 5 Modular Dev Kit:

SD Card: https://releases.rocketboards.org/2025.08/gsrd/agilex5_mk_a5e065bb32aes1_gsrd/

QSPI: https://releases.rocketboards.org/2025.08/qspi/agilex5_mk_a5e065bb32aes1_qspi/

Agilex 5 Premium Dev Kit:

SD Card: https://releases.rocketboards.org/2025.08/gsrd/agilex5_dk_a5e065bb32aes1_gsrd/

QSPI: https://releases.rocketboards.org/2025.08/qspi/agilex5_dk_a5e065bb32aes1_qspi/

I will fix this in our GSRD pages.

Related to the need of wipe the SDCard, this is only needed when building the binaries using the GSRD flow. This happens because the U-Boot SPL tries to find the u-boot.itb from the different boot devices starting with the SDCard. If you look at the HPS GHRD Linux Boot Examples page (https://altera-fpga.github.io/rel-25.1.1/embedded-designs/agilex-5/e-series/modular/boot-examples/ug-linux-boot-agx5e-modular/#boot-from-sd-card), this line changes the list of devices in which it will try to boot from, keeping only mmc, which corresponds to the SD Card.

sed -i 's/u-boot,spl-boot-order.*/u-boot\,spl-boot-order = \&mmc;/g' arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi

Related to the errors that you are seeing when building the binaries, it's possible that a package could be missing in the WSL2 environment when building the RootFS, but what is weird is that in this page https://altera-fpga.github.io/rel-25.1.1/embedded-designs/agilex-5/e-series/modular/boot-examples/ug-linux-boot-agx5e-modular, you just use the rootfs in the Linux boot stage and shouldn't affect that you see something on the serial console. The U-Boot SPL is the first binary that HPS executes and this is included as part of the bitstream provided to the system. This bitstream includes the hardware design(.sof) and the SPL(.hex):

In the case of booting from SD Card:

In the case of Booting from QSPI: 

If the hardware design(.sof) and the SPL(.hex) were created correctly, you should be able to see an output from the serial console. here you also need to double-check that in your devkit, the msel is set to QSPI so it can read the bitstream from the QSPI.

If you have problems generating the RootFS, you can get this directly from the Pre-Built binaries included in the correct paths provided above.

Thanks

Rolando

[BrianSune_Froum]

@RolandoS_Altera 

My questions are related to this ticket title SD Card Boot on latest version of 2025.01 or 2025.04.

If not wrongly understood the U-Boot had been changed since 2025

My original question : community.intel.com/t5/Intel-SoC-FPGA-Embedded/SD-Card-Boot/m-p/1714327#M3341

So unless Altera drop any support on C5,A5 I cannot see the default config can work proper on the 2024 or previous spl configurations.

[BrianSune_Froum]

@RolandoS_Altera 

The last comment is wrongly written.

So unless Altera drop any support on C5,A5 I cannot see the default config can work proper on the 2025 same as previous 2024 or even older version of spl configurations.