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Hi all
I've identified a strange behaviour in Simulation. Not sure if it my implementation or if it specific to the simulation.
I've a counter implemented with a Binary Adder to perform X + 1 operation.
with 3-bit binary adder its work, more than 4-bit I detect an X + 2 operation (or two X + 1).
I've create a test bench only for component implement this Adder, it appear correct. but my " End to End " test bench fails.
This project is published in Github and I've made a markdown description with screenshots + explainations of the Test Flow, here : FPGA-LEDs-Racer-/docs/sim_counter_problem.md at main · KerCrafter/FPGA-LEDs-Racer-
Thanks
Link kopiert
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After few experimentations, I've isolate the breakpoint.
it work fine with 14 LEDs, and problem appears from 15 LEDs are implemented. These 2 test cases are 4-bit binary adder.
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Hi,
Probably the overflow issue. If for 3-bit binary adder, use 7 leds got any issue?
For 15 and onwards leds, if use larger bit binary adder got any issue?
Probably need to take some precautious to take care the overflow issue.
Thanks,
Regards,
Sheng
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Hi Sheng,
I've create a test bench specificly for the WS2812B Driver, it's really correct, I've stress tested with +5000 WS2812B LEDs.
I don't know why my end to end test bench fails, then I've test independently each components around...
I think a solution to continue to develop the features could be isolate the 'WS2812B Driver' of this Project.
In all case, from the FPGA device (Cyclone IV E - DE0 Nano) it seems work correctly.
But I think I continue to monitor this issue.
Thx
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