Intel® Software Guard Extensions (Intel® SGX)
Discussion board focused on hardware-based isolation and memory encryption to provide extended code protection in solutions.

PF, GP fault in enclave



the sgx programming reference says that EXITINFO field can support #PF #GP exceptions if SECS.MISCSELECT.EXINFO = 1.  In the section 2.7.2 about SECS.MISCSELECT field, If CPUID(EAX=12H, ECX=0):EBX[31:0]=0, SECS.MISCSELECT field must be all zeros.  I have checked almost all of our lab's computers supported SGX. They are EBX=0. so they must set this field zeros.  otherwise, the SGX driver will report error.

So, is there some cpus to support this features now? In the paper “SGX-LAPD: Thwarting Controlled Side Channel Attacks via Enclave Verifiable Page Faults”,  their experiments use core i5-6200U to support the page fault exception inside enclave. But I don't have this cpu, I can't test it.

How can I get the details of each cpuid's result?  Has intel  provided a database to let me see the cpuid results for different leafs about each cpu?


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