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What's the order of the extended states saved in XSAVE area of the SSA frame?

Shujie
Beginner
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If the CPU supports multiple extended features and used by the enclave, I wonder in which order the related states will be stored in the SSA frame?  

The order of the general purpose registers stored in the SSA is well documented. Yet,  I cannot find any  material that talks about the details of XSAVE of the SSA frame.

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JesusG_Intel
Moderator
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Hello Shujie,


The information on how SGX interacts with processor extended states is in section 41.7 Interactions with the Processor Extended State and Miscellaneous State of Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3D: System Programming Guide, Part 4. You will find other references to XSAVE and the SSA in sections 39.4.1 AEX Operational Detail, 41.3.4 Interactions of Enclave Execution with Segmentation, EENTER - Enters an Enclave, ERESUME - Re-Enters an Enclave.


Sincerely,

Jesus G.

Intel Customer Support


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JesusG_Intel
Moderator
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Hello Shujie,


The information on how SGX interacts with processor extended states is in section 41.7 Interactions with the Processor Extended State and Miscellaneous State of Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3D: System Programming Guide, Part 4. You will find other references to XSAVE and the SSA in sections 39.4.1 AEX Operational Detail, 41.3.4 Interactions of Enclave Execution with Segmentation, EENTER - Enters an Enclave, ERESUME - Re-Enters an Enclave.


Sincerely,

Jesus G.

Intel Customer Support


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Shujie
Beginner
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JesusG_Intel
Moderator
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This thread has been marked as answered and Intel will no longer monitor this thread. If you want a response from Intel in a follow-up question, please open a new thread.


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