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Dear Intel Support Team,
I am writing to clarify a technical requirement outlined in your official SGX/TDX enabling documentation. Specifically, regarding the memory population rules stated below:
“At minimum, all slot 0's of all Integrated Memory Controller (IMC) channels for all installed CPUs must be populated (i.e., 8 DIMMs per populated CPU socket, at least). DIMM population must be symmetric across IMCs.
The following figure shows possible populations per populated CPU with 8 or 16 DIMMs...”
We seek clarification on the following points:
DIMM Capacity Requirements:
Does the requirement for populating 8 or 16 DIMMs impose specific restrictions on DIMM capacity (e.g., 16GB/32GB/64GB)?
For example, is it permissible to use mixed-capacity DIMMs (e.g., 16GB and 32GB modules) across slots, provided the total count and symmetry requirements are met?
Or must all DIMMs be identical in capacity?
Capacity Constraints (if applicable):
If capacity restrictions exist, are there minimum capacity thresholds or capacity combination rules (e.g., per-DIMM minimum capacity, channel-level uniformity)?
This clarification is critical for our hardware selection in multi-CPU server configurations. Your detailed guidance would be greatly appreciated.
Thank you for your support!
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