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I would like to know which CXL degraded modes Emerlad Rapids supports. We are having an issue with CXL FPGA IP interfacing with Emerald Rapids. The CXL ALMP negotiation only brings up the CXL.io virtual channel and CXL.mem/cache virtual channel does not come up.
Does Emerald Rapids support:
8 GT/s degraded
16 GT/s degraded
8x lane degraded
4x lane degraded
2x lane degraded
1x lane degraded
and
any combination of the above if any?
If we know which CXL physical parameters are supported, it would help us tremendously.
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Hello j_falchion,
I hope this message finds you well.
Thank you for contacting Intel Customer Support!
Regarding your request, we kindly ask that you review the datasheets linked below, as they may address your queries. Please note that while the title references the 4th Gen Intel® Xeon® Scalable Processor Family (Codename Sapphire Rapids), the document also includes information on the 5th Gen Intel® Xeon® Scalable Processor Family (Codename Emerald Rapids).
4th Gen Intel® Xeon® Processor Scalable Family, Codename Sapphire Rapids - Data Sheet Volume 1: https://edc.intel.com/content/www/us/en/secure/design/confidential/products-and-solutions/processors-and-chipsets/eagle-stream/sapphire-rapids-datasheet-vol-one/
4th Gen Intel® Xeon® Processor Scalable Family, Codename Sapphire Rapids - Data Sheet Vol. 2 Registers: https://edc.intel.com/content/www/us/en/design/products-and-solutions/processors-and-chipsets/eagle-stream/4th-gen-xeon-processor-scalable-family-code-name-sapphire-rapids-data/
If you have any further questions or need additional assistance, please feel free to reach out to us.
Thank you & Best Regards,
Ragulan_Intel
Intel Customer Support Technician
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Thank you! That is very helpful.
Do you have the same document for Granite Rapids and Clearwater Forest?
I'd like to know the same information for those two platforms regarding CXL.
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Hello j_falchion,
Greetings!
Please note that full datasheets for Granite Rapids and Clearwater Forest are not currently available. However, you may find the following resources helpful:
- Intel® Xeon® 6 Processor Family Product Brief: https://cdrdv2.intel.com/v1/dl/getContent/845771?explicitVersion=true
- Intel® Xeon® Scalable Processors Datasheet, Vol. 1: https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/2nd-gen-xeon-scalable-datasheet-vol-1.pdf
- Intel® Xeon® Processor Scalable Family Datasheet, Volume Two: Registers: https://www.intel.com/content/www/us/en/content-details/614073/intel-xeon-processor-scalable-family-datasheet-volume-two-registers.html
Additionally, you can explore our Resource and Documentation Center for more materials. Please note that not all documents are publicly accessible. To view confidential content, you will need a privileged account with Intel’s RDC. You can apply for access by following the instructions here: https://www.intel.com/content/www/us/en/support/articles/000058073/programs/resource-and-documentation-center.html
Important Notes:
- Approval for a privileged account may take up to 2 weeks.
- A valid Corporate Non-Disclosure Agreement (CNDA) is required to access RDC content. If you do not have an active CNDA, please contact your Intel® representative or distributor for assistance.
Please let me know if you need help with the application process or have any other questions.
Thank you & Best Regards,
Ragulan_Intel
Intel Customer Support Technician
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Thank you! Unfortunately those links are not helpful at all. I just need the equivalent information for Granite Rapids and Clearwater Forest here:
Is there a way to find the information from the link above for Granite Rapids and/or Clearwater Forest other than from the datasheet? We just need information to make sure that the server we plan to order supports the CXL implementation in FPGA we have.
In addition, we tuned our FPGA to x8 lanes and 8 GT/s, which should be supported by Emerald/Sapphire Rapids, however, the ALMP negotiation process still gets stuck. Do Emerald/Sapphire Rapids support x8 lanes at 8 GT/s? Note: The datasheet is ambiguous, because by saying it supports x8, it could mean it only supports that number of lanes for 32 GT/s.
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Hello j_falchion,
Greetings!!
Thank you for the update. Please allow us some time to review this we will get back to you soon.
Best Regards,
Vishal Shet P
Intel Customer Support Technician
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Hello j_falchion,
Greetings!
We have share the respond via email to you regarding the requested information.
Looking forward to hearing back from you!
Best Regards,
Azhari_Intel
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Hi Azhari,
Thank you for your e-mail. I have 1 further clarification regarding degraded mode. You mentioned degraded mode working at x8 and 8 GT/s for CXL.io specifically. What about for the CXL.mem channel? Maybe ALMP negotiation is getting stuck because the link parameters are not supported by CXL.mem. Please check if CXL.mem works with the following parameters:
x8 + 8 GT/s
x16 + 8 GT/s
x8 + 16 GT/s
x16 + 16 GT/s
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Hello j_falchion,
Greetings!!
Thank you for the update. Please allow us some time to review this we will get back to you soon.
Best Regards,
Mohammed Ali CM
Intel Customer Support Technician
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Hello j_falchion,
Greetings!
Just wanted to follow up with you regarding the reported issue.
We have shared the respond via email to you regarding the requested information.
Please let us know if you have any further concerns.
Looking forward to hearing back from you!
Best Regards,
Azhari_Intel
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Hi j_falchion,
Good day to you.
Since we have not seen an update, we will be closing this forum case from our end.
We hope that the information our team had shared earlier via email had resolve the issue you were facing.
Nonetheless, if any additional information is needed, please feel free to submit a new question as this thread will no longer be monitored.
Best Regards,
Azhari_Intel
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