Hi Intel Support,
I'm looking into the IOMMU performance counters on 3rd Gen Intel Xeon Processor ICE LAKE server. We note that, unlike previous versions, which provided IOMMU Page Walk Cache misses, the Intel PCM-IIO now provides the number of hits statistics. However, from our experiments, we found it is hard to interpret these counter values. We have the following three questions:
- There is one entry named "4K cache hit". Is it an extension cache of the IOTLB if the IOMMU uses a 4-level paging structure?
- We have observed that with IOMMU strict mode, IOPS = 4K cache hit << IOMMU memory access, while 512G/1G/2M cache hits are all zeros. From the manual, we learned that IOMMU memory access means there is a miss in the cache lookup and sends out memory fetches. Given these, we are confused whether these cache hit counters are reporting cache hits or cache misses?
- Could you explain the ICE LAKE's IIO counters in more detail? How could we calculate the page table walk cache misses from the counters provided?
We appreciate any support/help or explanations on the above questions. Thank you!
