Intel® Xeon® Processor and Server Products
Intel® Xeon® Processors, Data Center Products including boards, integrated systems, and RAID Storage
Comunicados
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
5186 Discussões

LMT missing some of the Lanes data

DiJin
Principiante
2.035 Visualizações

Hello,

 

I was using LMT 0.77 version to test CPU RX with 5 loops on Ubuntu 22, but after the test is done, there is some lanes data missing on some slots, and the missing lanes are random.

I searched on the manual, and find this:

 

Failure occurs (Read at the Margining Lane Status Register is not the
expected), that is, “10 ms has passed since ‘Report SetErrorCountLimit’
command was issued. Exiting Margining”.

 

But didnt find any further information, Do you know if there is any methods to solve this issue?

 

Thanks,

Di

0 Kudos
5 Respostas
Caguicla_Intel
Moderador
1.974 Visualizações

Hello Di,

 

Thank you for posting in Intel Communities.

 

Could you provide the model number of your CPU and details about your system? Also, would you be able to share screenshots of the tests that you're performing?

 

Best regards,

 

Caguicla C.

Intel® Customer Support Technician


DiJin
Principiante
1.957 Visualizações

Hello Caguicla,

Thank you very much for the reply. The CPU is SRF SP, the system is from customer side, but we do see this issue from different customers. I did see the similar issue from ICX CPU as well.

The test is to get the CPU RX margin, and loop for 5 times. 

I attached the two fail signature in the screenshot, and also from the data result screenshot, you could see only the last loop has all the four lanes data. some lanes data are missing in the first 4 loops.

We also test SSD RX 5 loops as well, SSD RX works fine.

 

Thanks,

Di

Caguicla_Intel
Moderador
1.919 Visualizações

Hello Di,

 

Appreciate your swift reply.

 

I'll review this request internally and provide you with an update as soon as possible.

 

Best regards,

 

Caguicla C.

Intel® Customer Support Technician


Caguicla_Intel
Moderador
1.894 Visualizações

Hello Di,

 

Thank you for your patience.

 

I'll direct this request to the relevant team for further assistance. Please await their reply in this conversation thread.

 

Best regards,

 

Caguicla C.

Intel® Customer Support Technician


Fikri_Intel
Funcionário
1.833 Visualizações

Hi DiJin,


Kindly be informed, in reference to your question about the PCIe Margining Tool, please visit, register, and submit your inquiry on our Intel® Developer Zone website for further peer-to-peer assistance on this matter:

https://www.intel.com/content/www/us/en/forms/developer/standard-registration.html


We will proceed in closing this thread. If you need any additional information, please submit a new question as this thread will no longer be monitored.



Regards,

Fikri O.


Responder