PCIe MMIO Poor Access Performance

[Shunyu]

I'm testing my FPGA with PCIE4.0 X16 on Intel Xeon 6438Y+, the theoretical bandwidth is 32 GBps per direction. If I use DMA method to perform access, it can be achieved to 27GBps, which is quite reasonable. But when I try to use MMIO via UIO to access BAR space, the highest bandwidth is only 3.75 GBps.

I have tried consecutive vmovntdqa, vmovapd, movdir64b, memcpy(), and I use ioremap_wc() in kernel driver to map a 4MB Write Combine space.

[NormanS_Intel]

Hello Shunyu,

Thank you for posting in the community!

To ensure you receive the most specialized assistance, we have a dedicated forum that addresses these specific concerns. Therefore, I will be moving this discussion to our Server Forum. This will allow our knowledgeable community and experts to provide you with timely and accurate solutions.

Best regards,

Norman S.

Intel Customer Support Engineer

[Ragulan_Intel]

Hello Shunyu,

Greetings!

As pertaining to the query you have, kindly reach out to the FPGA community and post question on the appropriate subforum topic.

Intel Community - FPGAs and Programmable Solutions 

Thank You & Best Regards,

Ragulan_Intel