Frequencies of the L1, L2, L3 caches.

[СБело2]

Need answer from employee of company Intel.

10-20 years ago caches of processor has that features:

- cache L1 integrated in processor, have smallest size and speedest frequency;

- cache L2 integrated in motherboard, have frequency = frequency of data bus. Biggest than L1, but many slowly.

What features have caches of processors now (i3 and newer)? I have 3 answers, need faithfull:

1. L1 < L2. L2 < L3. L1 speedest L2, L2 speedest L3.

2. L1 < L2. Frequency L1 = frequency L2 = frequency of processor's core. Frequency L3 < L1.

3. L1 < L2. Frequency L1 = frequency L2 = frequency of processor's core. Frequency L3 = L1.

[Allan_J_Intel1]

I am currently researching on this issue. As soon as I can, I will send you a message with my findings. Thank you for your patience and understanding.

Allan.

[СБело2]

Addition: maybe influences for speed caches that value: CAS-latency as decelerating, analogy RAM.

For example: frequency L1 = L2. But latency L1 < latency L2. Conclusion: L1 fastest L2.

[СБело2]

I got that:

- Intel. Intel® 64 and IA-32 Architectures Optimization Reference Manual: p,2-18, chapter 2.2.5.1, table 2-11.

Frequency L1 = L2 = L3. But latency L1 < latency L2 < latency L3.

L1 fastest (latency 4), L2 slowly (latency 12), L3 lowest (latency 26-31).

[Ronny_G_Intel]

Hi Sergey_85,

Intel(R) Core(TM) i7 / Intel(R) Core(TM) i5 / Cache Hierarchy:

The first level cache consists of a 32K L1 data cache and a 32K L1 instruction cache with one cache allocated per core. The second level cache is a high speed 256K cache for data and instructions with one cache allocated per core. The third level cache is a 8Mb inclusive cache logically shared across cores for Intel(R) Core(TM) i7 5xxx processors and a 6Mb inclusive cache shared across cores for the Intel(R) Core(TM) i5 5xxx processors.

I hope this helps,

[Ronny_G_Intel]

In addition to that: Intel(R) Core(TM) i3 Cache Hierarchy:

The first level cache consists of a 32K L1 data cache and a 32K L1 instruction cache with one cache allocated per core. The second level cache is a high speed 256K cache for data and instructions with one cache allocated per core. The third level cache is a 3Mb (Core i3 41xx/T) and 4Mb (Core i3 43xx/T) inclusive cache logically shared across cores.

I missed that part on my original answer.

Regards,