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16-bit shift left 2 register in VHDL

Altera_Forum
Honored Contributor II
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Ok, so I have a shift register (code below). But I need a shift left 2 register. So would I simply put "reg <= reg (14 downto 0) & '0' & '0';" ? Or do I need to do the shift process twice? I need help ASAP...any help would be great. 

 

entity shiftreg is 

Port  

(  

en : in STD_LOGIC; 

clock : in STD_LOGIC; 

reset :in std_logic; 

data_i : in STD_LOGIC_VECTOR (15 downto 0); 

shift : in STD_LOGIC; 

data_o : out STD_LOGIC 

); 

end shiftreg; 

 

 

architecture Behavioral of shiftreg is 

 

signal reg: std_logic_vector (15 downto 0); 

 

begin 

 

process (clock, en,reg,reset) 

 

begin 

 

if reset<='1' then 

reg<=data_i; 

elsif (clock'event and clock <='1' ) then 

if (en <='1') then  

reg <= data_i; 

elsif (en<='1' and shift<='1') then 

reg <= reg (14 downto 0) & '0'; 

end if; 

end if; 

end process; 

 

data_o <= reg (15); 

end Behavioral;
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Altera_Forum
Honored Contributor II
1,414 Views

"reg <= reg (14 downto 0) & '0' & '0' wont work because you're trying to assign 17 bits to a 16 bit vector. "reg <= reg (13 downto 0) & '0' & '0'" would work. 

 

Also, you have put <= in all the if conditions when you just mean =
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Altera_Forum
Honored Contributor II
1,414 Views

Multiply by 2 gives the result of left shift by 2......

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Altera_Forum
Honored Contributor II
1,414 Views

multiply by 2 gives left shift by 1. But multiplication isnt appropriate, because he has no numerical values.

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Altera_Forum
Honored Contributor II
1,414 Views

 

--- Quote Start ---  

multiply by 2 gives left shift by 1. But multiplication isnt appropriate, because he has no numerical values. 

--- Quote End ---  

 

 

 

she.  

 

Thanks! I got it working...just changed it to (13 downto 0).
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