I have a current design with SDRAM ( MT48LC4M32B; 1Mx32x4) but designed for a DSP (ADS 21161).
Is was planed from the very beginning also to test with a NIOS by omitting the DSP.
My problem is that the DSP is a pure 32 bit processor (no 8 bit access to the RAM …) and
so the layout has all the “DQM[3..0]” connected together. (
http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif … yes, I know it’s not okay …
http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif )
These 4 lines are a kind of byte-select, especially for write accesses.
My question is, has anybody an idea to run this design with a NIOS2 (Cyclone 1C20)
without the ability to write (read) to a specific byte?
From my point of view the heaviest problem is to convince the compiler only to address
the variables LWORD aligned. By the way, a NIOS2 with this SDRAM in a 8 bit mode is up and running, but not very efficient…
Thanks for any suggestions.
Frank
