AXI4 DMA Master Error

[Manprocoder]

Hi expert,

I am building SoC system that includes components as follows:

+ CPU

+ onchip_memory_2_0

+ onchip_memory_2_1 (source address)

+ onchip_memory_2_2 (destination address)

+ IP (Active Ascon) has AXI4 DMAC 

As program runs at simulation mode,  read burst request runs well, but write burst always encounters problem (awready is always "0" logic level), so DMAC always wait slave, leading 

my system to be stuck.

Could you clarify it to me? Thanks you so much.

Attached image

[Manprocoder]

Hi @SueC_Altera,
Sure. I have a strong desire to view your design for reference.

[SueC_Altera]

Hi Manprocoder,

Please see the design attached. I hope it helps!

Sue

[BoonBengT_Altera]

Hi @Manprocoder,

Good day, just following up on the previous clarification.

Do let us know if you have further clarification once you managed to look at the design provided.

Hope to hear from you soon.

Best Wishes

BB

[BoonBengT_Altera]

Hi @Manprocoder,

Greetings, as we do not receive any further clarification/updates on the matter, hence would assume challenge are overcome.

Please login to ‘ https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. For new queries, please feel free to open a new thread and we will be right with you. Pleasure having you here.

Best Wishes

BB