Agilex™ 5 FPGA E development Kit NIOS Design

[SDavi9]

Is there a development kit design, preferably in VHDL, for the Agilex™ 5 FPGA E development Kit that implements a NIOS II Tx and Rx using the FMC connector and an external optical device ? 

[sstrell]

If you find anything current, it will be for Nios V since Nios II has been obsoleted.

[SDavi9]

Thank you for your reply !

Is there then a NIOS V design that does this ?

[JingyangTeh_Altera]

Hi

Sorry that we do not have any VHDL only example design for interfacing with the Nios V TX and RX on FMC connector.

However we have a Hello World Example Design Application running on top of the HAL API.

This method will be the best method on interfacing with any IP using the Nios V.

Below link might help kick you off in the right direction

https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/24.3.1/niosv_g/niosv_g_helloworld/docs/Agilex%E2%84%A2_5_FPGA_Nios%C2%AEV_g_Processor_Helloworld_Design.pdf

Regards

Jingyang, Teh

[SDavi9]

Dear Jingyang,

Thank you so much for getting back to me so quickly. I will check it out. Are the top levels in VHDL ?

Best regards

Shmuel 

[JingyangTeh_Altera · Accepted solution]

Hi

Yes, the top levels are in VHDL.

They are just simple connection for the Nios V Processor.

Regards

Jingyang, Teh

[JingyangTeh_Altera]

Hi

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Jingyang, Teh