About SDRAM clock ! ?

[Altera_Forum]

Can I use separate clock for SDRAM ? 

For Example CPU- 50 MHZ  SDRAM - 100 MHZ  Is it possible ?

[Altera_Forum]

I have tried that before but it didn't want to work. Would be great if it did :-)

[Altera_Forum]

That should have worked (assuming you use the clock crossing adapters in SOPC Builder). The million dollar question is what did you delay the clock with (if you speed up the clock you want to keep a constant time delay but in terms of degrees it should have doubled from what it was at 50MHz). So the phase for the SDRAM clock at 50MHz was probably -72 ish, and so this becomes -144 degrees at 100MHz (I'm assuming a Nios development board here). 

 With that said, I don't recommend running a Nios processor at a different clock speed as memory (being able to run the CPU and memory at the same speed is one of the advantages an embedded processor has over your PC sitting on your desk). Depending on what's in your system I could probably recommend a mix that will give you the highest performance possible (i.e. need more info).  Cheers

[Altera_Forum]

I agree with BadOmen -- you can certainly run CPU & SDRAM at different speeds, but if the CPU is using that memory for instructions or (primary) data, then they should be on the same clock domain. Besides, Nios II & the SDRAM controller will typically run at the same f-max, so I don't see why you'd want to run the processor slower? 

 The reason for this is that the clock-crossing logic adds delay; while you may be running one interface faster, it takes longer to access it.   Now, there is a case I can think of where running the memory at a different speed than the CPU would be desirable: if you have a piece of custom hardware which has an f-max much higher or lower than tha processor (and therefore is driven by its own clock) and it needs to access memory at maximum bandwidth -- then you would want to run your custom hardware and memory controller with the same (different from the CPU) clock.  Where the clock domain crossing feature is most powerful is for a system with one or more very slow interfaces that are not in the data path -- that way you can keep your processor/memory/other logic running as fast as possible and use a separate clock for the slower logic.

[Altera_Forum]

What I wanted to do was to run a NIOS core at 50MHz and VGA from the same SDRAM block. I don't want the NIOS to add wait states. Sitting with 133MHz (100Mhz from the core) memory seems a waste. So I want to run my 50Mhz NIOS at 50MHz, with the best memory performance, and use the rest of the bandwidth for something else. 

  Will try and add some more delay. Thought the 72 degrees would be enough. Will play with that. My thought was that the avalon bus would handle everything. Seeing that you can run 2 or more NIOS CPUs from the same memory, running at the same speed it makes sense that running 2 or more CPUs/masters from faster peripheral (like 100MHz SDRAM) would be possible.   VictorS

[Altera_Forum]

Running the processor at a different clock speed than its program memory will add domain crossing delays that will make your processor run much slower, worse than running everything at 100MHz. Moreover, SDRAM are not suitable for the multiple clock domain architecture without having complicated memory controllers capable of burst access. 

If you have a bandwidth hungry peripheral like a video controller, a better solution is to play with the bus priorities in SOPC Builder and if that is not enough, consider adding a dedicated video memory chip.