About external SRAM

[Altera_Forum]

Hi, 

 I have problems with my NIOS and external SRAM. any of your help are appreciated. the case is as following:  I have a board built of my own, the board contain a Stratix chip EP1S20F780, and 4 SRAM chips , the SRAM are Cypress's CY7C1021CV33, which is a 64K X 16 bits SRAM, other than the IDT 71V416 SRAM. in my board 2 chips are linked each other to form a 32bits wide SRAM. so, from the FPGA's view, there 2 SRAMs in my board. each of them are 32 bits of width. only SRAM's OE_n, WE_n, ADDRESS and DATA signals are connected to EP1S20F780. all other SRAM's pins are connected to either VCC or GND.  my problem is: how to connect these 2 SRAMs to my NIOS2?  I have tried as the following steps, but tured to be a failure.   1) I wrote a Verilog HDL file about signals that need to be used between the avalon tri_state slave and the SRAM. 2) in the SOPC builder, I chose create new component. 3) in the new window, I add the new Verilog HDL file 4) chose interfaces as avalon tri_state slave type  But, there occurs the problem now, I can not change the data ports to inout. so, there shows the error message:  avalon_tristate_slave_0: slave has write signals but no data signal avalon_tristate_slave_0: slave has read signals but no data signal avalon_tristate_slave_0: slave must have a read or write interface or support interrupts  I have no idea of how to cope with this problem. can anyone give me a tutorial of how to add an external SRAM (other than the one on the development kits, i.e. IDT 71V416) to my NIOSII?  Thank you in advace.  regards gong xuechun

[Altera_Forum]

Hi, gxc 

 If you want ro creat a component with your own verilog file, I suggest that you'd better not choose the tri_state type slave. Because the compnent you creat is put into the FPGA, but not outside the FPGA. And the compnent should has two data interface including wr_data and rd_data interface, which respond to the signal of the avalon bus.

[Altera_Forum]

try the following: 

 add the ram as user logic  (remark one userlogic for both ram chips,  this is necessary to get one block of memory for system library properties)  I think your address width is 17 (128k=2*64k*32bit)  PORTNAME WIDTH DIRECTION SHARED TYPE address 17 input yes address  write_n 1 input yes write_n read_n 1 input yes read_n data 32 inout yes data chipselect_n 1 input --- chipselect_n be_n 2 input yes byteenable_n remark: not needed   add external logic in top.bdf (one not and two ors's) to generate the two different CS signals  SRAM_CS0_N = SRAM_CS or A16 SRAM_CS1_N = SRAM_CS or (not A16)

[Altera_Forum]

...or you could take a look at Altera's existing SRAM component, copy it to a new location (with a different name) and modify it to suite your needs. 

 - slacker

[Altera_Forum]

Dear Experts: 

  Thank you for your help.  I think I should first give more detail information here. so you can know what wrong with me more exactly.  I am a beginer in using niosII. we have not purchase any development kit, but fortunately, we have a stratix FPGA board for other applications. there is a Stratix EP1S20F780 and four chips of Cypress CY7C1021CV33(64K X 16 bits) on it. the FPGA is connected to these 4 SRAMs. the SRAMs are asynchrous SRAMs, which has ADDRESS(16), DATA(16), CE_n(1), WE_n(1), CS_n(1), CE_n(1), BHE_n(1), BLE_n(1) , OE_n(1) and VCC, GND ports. we dived these 4 SRAMs to two groups, each group is consists of 2 chips. alougth all SRAMs are 16 bits of width, but we use 2 chips to width expand each group to 32 bits of width. the FPGA connect with SRAMs ADDRESS(2 groups: A0[15:0], A1[15:0]), DATA(2 groups: DATA0[31:0], DATA1[31:0]), OE_n(2 groups: OE_n0, OE_n1), WE_n(2 groups: WE_n0, WE_n1). we connect all remain SRAMs ports to fixed levels, either VCC or GND. CS_n connect to sgnal GND, always select; BHE_n and BLE_n connect to signal GND too, so, all 4 Bytes are always selected.   When I first touch nios, I use FPGAs onchip memories as nios' memory, and run the helloword program. it success!  But the onchip memory's capacity is limited. so, I try to use the SRAMs on my board.   1st, I add IDT71V416 and avlon tri-state bridge and run Helloword program, it did not work.  2nd, I write a Verilog HDL module to list all the used ports of the SRAM, but in this way, I can not make it a tri-state slave. because alougth i define the DATA ports as inout in the Verilog file, but in the SOPCB, I found these DATA ports remain input ports. so, the SOPCB give following error message:  avalon_tristate_slave_0: slave has write signals but no data signal avalon_tristate_slave_0: slave has read signals but no data signal avalon_tristate_slave_0: slave must have a read or write interface or support interrupts  So, my second attempt also failed.  My 3rd attempt did not use a verilog HDL file, I just open the Create new component, add signals and select interface in the create new component window. I added 4 signals. they are DATA, ADDRESS, READ_n, WRITE_n. after generate the system, I created a new project, in the project's top module, I wrote:  assign ADDRESS = NIOS_SYSTEM's ADDRESS[17:2]; assign OE_n = READ_n   after all these steps, I programmer the FPGA(using the .sof file), run helloword program, the result is:  nios2-terminal: starting in terminal mode (using ctrl + C to eixt) no "hello" message displayed.  by the way, I use the byteblaster not a USB cable.   thank you all. gong xuechun

[Altera_Forum]

you should use the chipselect signal, otherwise data can be unpredictably  

written to the ram !!!  you will need at least address,data,write_n,read_n,chipselect_n  I don't have any experience with the new "Create New Component", only with the  former way of "legacy components -> interface to userlogic", which is still  there.

[Altera_Forum]

Dear Fischer: 

  Thank you for your timely reply.  First, I should clarify alougth the SRAM chips CY7C1021CV33-10 used in my circuit board has CE_n, OE_n, WE_n, ADDRESS, DATA, BHE_n and BLE_n control signals. but in our circuit board, only OE_n, WE_n(combined R/W). ADDRESS, and DATA are connected to our FPGA(EP1S20F780C7) whereas CE_n, BHE_n and BLE_n (Byte lane enable) are fixed connected to GND.   I added the chipselect_n signal in my design as you told me in last post. but I still failed.  Here is what I did and what problems I met.   First, I open SOPCB, then open Component Editor. in the Component Editor, I created a Component, its name is CY7C1021CV33. under the Component Editor's signals button, I enter the following lines:  ram_write avalon_tristate_slave_0 write_n 1 input ram_address avalon_tristate_slave_0 address 16 input ram_data avalon_tristate_slave_0 data 32 inout ram_read avalon_tristate_slave_0 read_n 1 input ram_cs avalon_tristate_slave_0 chipselect_n 1 input  Under the interfaces button, I entered the following boxes:  Name: avalon_tristate_slave_0 Type: avalon_tristate_slave Slave addressing: memory can receive stderr/stdout: yes/no (both cases was examined) setup: 0 readwait: 0/1 (both cases was examined) writewait : 0/1 (both cases was examined) hold: 0   After all these, I push the "Finished" button. a component named CY7C1021CV33 is generated, this will close the component editor and the component CV7C1021CV33 is automatically appeared in the User Logic group.  In the SOPCB, I new a nios2 system. its name is "sram_test". in this nios2 system, first, I added a niosII processor, its clock is 50MHz, then I added a JTAG UART, a CY7C1021CV33 just generated, an avalon tri-state bridge. and linked the CY7C1021CV33 to the master. auto assign base address, then generated the NiosII system.  After the NiosII system was generated, I went back to the QuartusII software. I newed a project here. in the project's top level, I wrote the following in verilog HDL:  module external_sram(clk, reset_n, ram_address, ram_we, ram_oe, ram_data); input clk, reset_n; output [15:0] ram_address; inout [31:0] ram_data; output ram_oe, ram_rw;  reg [17:0] bridge_address; reg  sram_test my_sram_test(clk, reset_n, ram_cs,

[Altera_Forum]

Dear experts: 

 Thank you for your timely reply. First, I should clarify alougth the SRAM chips CY7C1021CV33-10 used in my circuit board has CE_n, OE_n, WE_n, ADDRESS, DATA, BHE_n and BLE_n control signals. but in our circuit board, only OE_n, WE_n(combined R/W). ADDRESS, and DATA are connected to our FPGA(EP1S20F780C7) whereas CE_n, BHE_n and BLE_n (Byte lane enable) are fixed connected to GND.  I added the chipselect_n signal in my design as you told me in last post. but I still failed. Here is what I did and what problems I met.  First, I open SOPCB, then open Component Editor. in the Component Editor, I created a Component, its name is CY7C1021CV33. under the Component Editor's signals button, I enter the following lines:  ram_write avalon_tristate_slave_0 write_n 1 input ram_address avalon_tristate_slave_0 address 16 input  ram_data avalon_tristate_slave_0 data 32 inout ram_read avalon_tristate_slave_0 read_n 1 input ram_cs avalon_tristate_slave_0 chipselect_n 1 input  Under the interfaces button, I entered the following boxes:  Name: avalon_tristate_slave_0 Type: avalon_tristate_slave Slave addressing: memory can receive stderr/stdout: yes/no (both cases was examined) setup: 0 readwait: 0/1 (both cases was examined) writewait : 0/1 (both cases was examined) hold: 0   After all these, I push the "Finished" button. a component named CY7C1021CV33 is generated, this will close the component editor and the component CV7C1021CV33 is automatically appeared in the User Logic group.  In the SOPCB, I new a nios2 system. its name is "sram_test". in this nios2 system, first, I added a niosII processor, its clock is 50MHz, then I added a JTAG UART, a CY7C1021CV33 just generated, an avalon tri-state bridge. and linked the CY7C1021CV33 to the master. auto assign base address, then generated the NiosII system.  After the NiosII system was generated, I went back to the QuartusII software. I newed a project here. in the project's top level, I wrote the following in verilog HDL:  module external_sram(clk, reset_n, ram_address, ram_we, ram_oe, ram_data); input clk, reset_n; output [15:0] ram_address; inout [31:0] ram_data; output ram_oe, ram_rw;  reg [17:0] bridge_address; reg ram_cs, ram_write, ram_read;  sram_test my_sram_test(clk, reset_n, ram_cs, ram_read, ram_write, bridge_address, ram_data);  assign ram_address = bridge_address[17:2]; assign ram_rw = ram_write | ram_cs; assign ram_oe = ram_read | ram_cs;  endmodule  Compile the project and generate the "external_sram.sof" file, then program the FPGA using this file.  After run the hello_world application. the following messages displayed:  nios-terminal: connected to hardware target using JTAG UART on cable "ByteBlaster II [LPT1]", device 2, instance 3.   warning: The JTAG cable you are using is not supported for Nios II systems. you may experience intermitent JTAG communication failures with this cable. please use a USB Blaster revision B cable or another supported cable. please refer to the file errata.txt included in the Nios II development kit documents directory for more information.  nios-terminal: Starting in terminal mode (control-C exits)  But the "Hello from my Nios II" is not come out.  I also consulted the errata.html in the development kit documents directory, it tells that: JTAG UART is unstable after device wide reset (SPR145501) , the workaround is turn off the Enable device wide reset setting in the Quartus II software.  Checking my Quartus II software's settings, the "Enable device wide reset" is in the "off" state.  So, I do not know where I was wrong. any help from you are appreciated.   best regards Gong Xuechun

[Altera_Forum]

try again to start a simple program from onchip memory, then try to use  

the memory view in the debugger, if you can access your external memory.

[Altera_Forum]

Yes, if I starting from a simple nios2 system with onchip memory, I can debug and trace my application. there is an arrow point to the 1st line of my source C code when I start debugging. But if run the same application in my nios2 system with offchip memory, then I can not debug and trace my application, all "Step Into, Step Over..." menus are grayed and not active, there is no any arrow point to my C source code. 

So, I think there sould be some wrong in my system with offchip memory. But I still do not even have a clue of where the wrong is.  Could you give any further advices. Thank you.   Gong Xuechun

[Altera_Forum]

first check if your hardware is ok 

 if you use the "onchip memory program", try to access the external sram from either  - "memory view in the debugger", you can write and read to your external memory from this window, - access your external sram with some small testcode   (write to sram address and read back)   if your hardware is ok, check the settings in SOPC Builder  "Nios II more CPU Settings" and system libray properties

[Altera_Forum]

hi:qxc! 

have you done that question?i am now meeting the same with you,i have tried the ways as them said,but i still failed!can you give me some ideas,thanks in advance!

[Altera_Forum]

I agree with Fischer! 

You should check off-chip memory if you can access it correctly!  Maybe your sram's speed can't meet your system clock, that says  Your sram is slower than nios2 cpu clock!

[Altera_Forum]

--- Quote Start ---  originally posted by yesdingsheng@Apr 17 2005, 08:47 AM hi:qxc!           have you  done that question?i am now meeting the same with you,i have tried the ways as them said,but i still failed!can you give me some ideas,thanks in advance!  --- Quote End ---    I have done the experiment using development board that the same as qxc have been described. I added the ram as user logic.My user logic interface file : module sraminterface(ram_data,ram_addr,ram_we,ram_oe); inout [31:0]ram_data; input [15:0]ram_addr; input ram_we,ram_oe; endmodule  and my project&#39;s top entity file: module sram(clk,rst,ram_addr,ram_oe,ram_we,ram_data); input clk,rst; output ram_we,ram_oe; output [15:0]ram_addr; inout [31:0]ram_data; sramsopc mysram(clk,rst,ram_addr,ram_oe,ram_we,ram_data); endmodule  my c file is: # include <stdio.h> int main() {  printf("hello from nios ii!\n");   return 0; }  During the experiment ,I encountered two problem: 1, In my user logic interface file , I set sram address width as 16bits,but in sopc bulilder generated file,it became to 18bits . 2,there is no warning or error but the string displayed on the nios2 console is not "Hello from Nios II!".just some strange code. I wonder what&#39;s happened.