Accessing inputs and outputs of a custom component

Altera_Forum · ‎12-24-2013

Hello every body;

I have created my custom compnent caled "cipher", it takes 2x128 bits input and produce one 128bit ouput, the component definition in system.h is:

#define ALT_MODULE_CLASS_Cipher_0 Cipher

#define CIPHER_0_BASE 0x201020

#define CIPHER_0_IRQ -1

#define CIPHER_0_IRQ_INTERRUPT_CONTROLLER_ID -1

#define CIPHER_0_NAME "/dev/Cipher_0"

#define CIPHER_0_SPAN 32

#define CIPHER_0_TYPE "Cipher"

My Quistions are:

1-what is the address of the inputs and outputs.

2-how can i access them if i want to pass and read the inputs and the outputs as 4x4 array.

Thanks.

Altera_Forum · ‎12-25-2013

--- Quote Start ---

1-what is the address of the inputs and outputs.

--- Quote End ---

CIPHER_0_BASE + offset

where 'offset' is whatever register addresses you have defined within your custom component (i.e. how you decode the 'address' on the Avalon-MM Slave port)

--- Quote Start ---

2-how can i access them if i want to pass and read the inputs and the outputs as 4x4 array.

--- Quote End ---

You can use IORD/IOWR macros to access the registers you have created one at a time.

Altera_Forum · ‎12-25-2013

Thanks Ted for your reply>

but I have an address span of 32 byte or (16 byte for each input), here what is the base address of the output ?

Altera_Forum · ‎12-25-2013

You need to take care of address in your custom component.Address will be as shown in below code.

//RTL Code for write logic

case({av_write,av_address[4:0]})

6'b1_00000 cipher_in1[31:0] <= av_wrdata;

6'b1_00100 cipher_in1[63:32] <= av_wrdata;

6'b1_01000 cipher_in1[95:64] <= av_wrdata;

6'b1_01100 cipher_in1[127:96] <= av_wrdata;

6'b1_10000 cipher_in2[31:0] <= av_wrdata;

6'b1_10100 cipher_in2[63:32] <= av_wrdata;

6'b1_11000 cipher_in2[95:64] <= av_wrdata;

6'b1_11100 cipher_in2[127:96] <= av_wrdata;

endcase

//RTL code for read logic

case(av_address)

0 : av_rddata <= cipher_out[31:0];

4 : av_rddata <= cipher_out[63:32];

8 : av_rddata <= cipher_out[95:64];

12 : av_rddata <= cipher_out[127:96];

endcase

//NIOS Code

//Cipher Input 1

IOWR(CIPHER_0_BASE,0x00,0x03020100);

IOWR(CIPHER_0_BASE,0x04,0x07060504);

IOWR(CIPHER_0_BASE,0x08,0x0b0a0908);

IOWR(CIPHER_0_BASE,0x0c,0x0f0e0d0c);

//Cipher Input 2

IOWR(CIPHER_0_BASE,0x10,0x03020100);

IOWR(CIPHER_0_BASE,0x14,0x07060504);

IOWR(CIPHER_0_BASE,0x18,0x0b0a0908);

IOWR(CIPHER_0_BASE,0x1c,0x0f0e0d0c);

Altera_Forum · ‎12-25-2013

--- Quote Start ---

Thanks Ted for your reply>

but I have an address span of 32 byte or (16 byte for each input), here what is the base address of the output ?

--- Quote End ---

You would need to review the custom component (Verilog/VHDL) you created and understand what address is supplied to it in order to read the 'output'.

It sounds like maybe you havent declared a wide enough address space to fit (3) 128-bit elements?

Altera_Forum · ‎12-28-2013

Thanks ted for your attentions;

I tried what you have illustrated and worked well with me, now, my custom logic takes 26 clk cycles to produce the output, how can i access the output just it finish processing the inputs.