Bug in SOPC?

[Altera_Forum]

Why IDT71V416 IP generate 32bit DataBus?Ignore it or I miss something. 

 My quartus and nios 's version is 5.1  In the SOPC ,I chose the SRAM IP IDT71V416 .The SOPC generate 32bits databus. While the IDT71V416 is 16 bits. Why????  I confused........ Bug in SOPC or need 2 IDT71V416,But I need only one.

[Altera_Forum]

--- Quote Start ---  originally posted by tommycp@Aug 25 2006, 10:26 AM why idt71v416 ip generate 32bit databus?ignore it or i miss something.  my quartus and nios &#39;s version is 5.1  in the sopc ,i chose the sram ip idt71v416 .the sopc generate 32bits databus.  while the idt71v416 is 16 bits. why????  i confused........                bug in sopc or need 2 idt71v416,but i need only one. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=17821)  --- quote end ---    --- Quote End ---    Altera&#39;s develop board has daul IDT71V416 to combin a 32bit data bus. So the sram core has a 32 bit data bus.

[Altera_Forum]

--- Quote Start ---  originally posted by tommycp@Aug 24 2006, 09:26 PM why idt71v416 ip generate 32bit databus?ignore it or i miss something.  my quartus and nios &#39;s version is 5.1  in the sopc ,i chose the sram ip idt71v416 .the sopc generate 32bits databus.  while the idt71v416 is 16 bits. why????  i confused........                bug in sopc or need 2 idt71v416,but i need only one. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=17821)  --- quote end ---    --- Quote End ---    Hi TommyCP,  a maybe possible solution for your problem in the "IP download folder"  Regards Frank

[Altera_Forum]

hi franky, 

  Thanks you ,and Could you show me how to get the IP,I can&#39;t find it.or is there some other way to solve this problem,such as ignore the data[16..31]or ......   Tommy

[Altera_Forum]

TO_BE_DONE

[Altera_Forum]

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif Fischer, 

Thank you help me again.    Does you just change the Pins generated by IP , without the IP inside.    I have seen the sch(\niosII\documents\nios_cyclone_1c20),which have two IDT71V416.So I wonder whether the IP work if I change the Pins (SOPC generate as you show)or I don&#39;t connect the IDT71V416 properly as the example show.   I thought the IP have its specific connection rules outside and it won&#39;t work if hardware connection goes wrong or not properly.   Thanks again. Tommy.

[Altera_Forum]

Anyone help me!

[Altera_Forum]

use component editor: 

you create a new component,  (interface description to an external component, not an IP), you get new signals in your top schematic to connect your SRAM, you have to connect your SRAM to work properly).   HDL Files : no hdl files  Signals Tab:  Name Interface Signal Type Width Direction  address avalon_tristate_slave_0 address 18 input data avalon_tristate_slave_0 data 16 bidir cs_n avalon_tristate_slave_0 chipselect_n 1 input wr_n avalon_tristate_slave_0 write_n 1 input rd_n avalon_tristate_slave_0 read_n 1 input be_n avalon_tristate_slave_0 byteenable_n 2 input clk avalon_tristate_slave_0 clk 1 input  Interfaces Tab:  Name: avalon_tristate_slave_0 Type: avalon_tristate_slave  Slave addressing: Memory (use dynamic bus sizing) Minimum Arbitration Shares: 1 Can receive stderr/stdout: No  Avalon Tristate Slave Timing: Setup: 1 , Read Wait: 1 , Write Wait: 1 , Hold: 1 , Units: cycles Read Latency: 0  SW FIlesw : no files  Component Wizard:  Component name: SRAM_512KBx16 Component Version: 1.01 Conponent Group: Memory   After generation you will get new signals in the top cpu symbol: cs_n_to_the_sram_512kbx16_0 maybe you get also write_n_to_the_sram_512kbx16_0  read_n_to_the_sram_512kbx16_0   then connect  cs_n_to_the_sram_512kbx16_0 --> RAM: \CS write_n_to_the_sram_512kbx16_0 --> RAM:\WE read_n_to_the_sram_512kbx16_0 --> RAM:\OE tristate_bridge_0_byteenablen[1] --> RAM:\BHE tristate_bridge_0_byteenablen[0] --> RAM:\BLE tristate_bridge_0_address[18..01] --> RAM: A[17..0] (two bytes) tristate_bridge_0_data[15..0] --> RAM:D[15..0]  (you can share the write and read signals with the tristate_bridge_signals: tri_state_bridge_0_writen and tri_state_bridge_0_readn,  by manually changing the ptf file (reinsert component in SOPC!)  or using additional logic in top schematic)

[Altera_Forum]

Thank you ,I will try.

[Altera_Forum]

Dear Fischer, 

 I met the same problem (My board only has 256kx16 sram) I built the the component as you said. But when I run NIOS II IDE(6.0) to build a project. I can&#39;t find the sram.dat file for simulator use.  But when I use the Memory-> IDT71v416 SRAM, NIOS II IDE will generate sram.dat for sumulator. (I had set the program code to sram)  Why ?! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif   thanks for yor help

[Altera_Forum]

sorry, don&#39;t know how to do this, 

perhaps try the 16 bit SRAM component from download section,  http://forum.niosforum.com/forum/index.php...=st&f=15&t=4645 (http://forum.niosforum.com/forum/index.php?act=st&f=15&t=4645)

[Altera_Forum]

Great! 

I ported it on my board and it work fine  http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif   Thanks