Cache bypass

Altera_Forum · ‎05-04-2006

Hello all,

I'm developing an application with two or more Nios II processors. There is a scheduller that select a thread to execute on a specific cpu. Any thread can run on any cpu. However, there is no support to any cache coherency mechanisms in Nios II, and I can't disable explicitly the cache.

To solve this problem, I thinking in use the bit-31 cache bypass provided in the Nios II/f core. So, I should set to one the most-significant bit (bit 31) of the resource address (that is used for more of one cpu).

Is there any way to do this for all addresses?

I changed the the address references in linker script file (generated.x for applications builded in Nios II-IDE):

From:

    sdram_UNUSED : ORIGIN = 0x01000000, LENGTH = 32
    sdram : ORIGIN = 0x01000020, LENGTH = 16777184
    __alt_data_end = 0x01100020; (used for stack)

To:

    sdram_UNUSED : ORIGIN = 0x81000000, LENGTH = 32
    sdram : ORIGIN = 0x81000020, LENGTH = 16777184 (bit-31 set to one)
    __alt_data_end = 0x81100020;

All the references were changed in .elf... but the nios2-download tool dowloaded the .elf at non valid address, and the nios couldn't execute it.

Do you know any way to do that?

Any another idea is welcome!!!

Thanks all.

Regards,

Maikon

Altera_Forum · ‎05-04-2006

Maikon,

Take a look at the content in <nios2_install>/documents/gnu-tools/gcc/Altera-Nios-II-Options.html.

In particular, I think you'd be interested in the

-mbypass-cache
-mno-bypass-cache

options, though there's other good stuff, in this page, as well. Whenever I'm looking for Nios II details, I always start at the <nios2_install>documents/index.htm webpage...and then I search on the Forum.

Cheers,

- slacker

Altera_Forum · ‎05-05-2006

--- Quote Start ---

originally posted by maikon@May 4 2006, 10:52 PM

hello all,

i'm developing an application with two or more nios ii processors. there is a scheduller that select a thread to execute on a specific cpu. any thread can run on any cpu. however, there is no support to any cache coherency mechanisms in nios ii, and i can't disable explicitly the cache.

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=15061)

--- quote end ---

--- Quote End ---

That's a known problem... If you want, take a look at the erika enterprise multicore support for nios 2 (http://www.evidence.eu.com/nios2) web page, we solved most of these issues related to multicore support in Nios II...

In any case, most Nios II designs are eterogeneous multicores, and migrating tasks over CPUs is not the most efficient thing to do, unless you are doing it for research purposes.

bye

Paolo

Altera_Forum · ‎05-05-2006

Thanks Slacker and Paolo,

I used the -mbypass-cache flag to compiler and linker. All references to ldw/stw instructions were changed to ldwio/stwio. In processors with a data cache, the ldwio/stwio instructions bypasses the cache.

This solves the problem!

Thanks!!