Changing HPS SDRAM parameters in Qsys need to rebuild the whole FPGA

[Altera_Forum]

I am investigating a issue with HPS SDRAM. What i am doing here is changing some HPS SDRAM parameter in Qsys and recompile HPS. 

My question is do i need to rebuild the whole FPGA to make the HPS change active? If not, then it will save us lots of time for debugging.  Thank you.

[Altera_Forum]

If I am not mistaken, you only need to regenerate the Qsys component --> that will regenerate the hardware-software handoff files (including the calibration needed for the HPS SDRAM). Then it is a matter of updating the preloader with the latest changes... (again, assuming you are using the bsp-editor tool to generate the preloader that calibrates the SDRAM)

[Altera_Forum]

Thank you, Sunshine. 

That is my guess too. Yes, i am using bsp-editor to update preloader.

[Altera_Forum]

No, I tried. If I just regen the HPS in Qsys, but do not recompile the whole FPGA, it turned out the hps_isw_handoff files are not updated at all....