I have a question related to the way how NIOS IDE (or the linker beneath it) does see ram for program/data allocation.
I have designed a nios II board with 3 external SRAM banks, they consist of 3 SRAM chips configured as User Logic each with separate chipselect, but all 3 giving me one continuous addressing space of 3 megabytes. Unfortunatelly, they are visible as separated to the NIOS IDE as 3 completely different ram areas: sram_bank0, sram_bank1, sram_bank2. When I configure the system library and have to assign where to put the program, ro data and rw data memory and I wish I could treat all these 3 ram chips as a one continues space to put all my stuff but I have to pick one of them instead.
One way to work around this would be to have one User Logic for all three chips with an external address decoder, using one chipselect and address line to generate secondary chipselects for each ram chip. But right now I have three user logic modules, each for one memory bank because not all three will be populated on my target board.
Is there a more elegant way to configure sram memory area of variable size and see it as one space in the IDE?
