Configure NIOS firmware burning interface

[ZhiqiangLiang]

Hi,

I would like to run NIOS II in FPGA. I am now use Cyclone 10 LP 10CL120.

I have a few questions:

1)  how to enable/configure UART burning interface in Quartus Platform Designer?

2) If I don't enable/config UART burning interface, is there any other way to burn firmware to NIOS on FPGA?

3) If I configure RAM and ROM size for NIOS, I don't know what is the maximum size I can set as I don't know what is the remained resource in FPGA?

4) in Platform Designer, if I create a New Component, it is very difficult to config "Signals & Inferfaces" in Compent Editor. For example, what is conduit?  how to config AXI4 Lite Slave interface?

5) if I enable/configure SPI or Ethernet, is the C driver enabled in Eclipse? how to enable the driver?

[JitLoonL_Altera]

Hi, 

1) how to enable/configure UART burning interface in Quartus Platform Designer?

• Open Platform Designer: Go to Tools > Platform Designer in Quartus Prime.
• Add UART Component: In the Platform Designer, add the UART component from the IP catalog.
• Configure UART: Set the parameters for the UART, such as baud rate, data bits, stop bits, and parity.
• Connect UART Signals: Connect the UART signals to the appropriate pins on the FPGA. Ensure the uart_tx and uart_rx signals are correctly mapped.

2) If I don't enable/config UART burning interface, is there any other way to burn firmware to NIOS on FPGA?

• JTAG Interface: Use the JTAG interface to program the FPGA. This is the most common method and is supported by Quartus Prime.
• Flash Memory: Program the firmware into flash memory and configure the FPGA to load the firmware from flash during boot.

3) If I configure RAM and ROM size for NIOS, I don't know what is the maximum size I can set as I don't know what is the remained resource in FPGA?

• Open Platform Designer: Go to Tools > Platform Designer.
• Add On-Chip Memory Component: From the IP catalog, add the On-Chip Memory (RAM or ROM) component.
• Set Memory Size: Configure the memory width and total size based on your requirements. The maximum size depends on the available resources in the FPGA.
• Check Resource Utilization: Use the Quartus Prime compilation report to check the remaining resources in the FPGA and adjust the memory size accordingly.

4) in Platform Designer, if I create a New Component, it is very difficult to config "Signals & Inferfaces" in Compent Editor. For example, what is conduit? how to config AXI4 Lite Slave interface?

• Conduit: A conduit is used to group signals that are not part of a standard interface. It allows you to create custom connections between components.
• AXI4 Lite Slave Interface: To configure an AXI4 Lite Slave interface, use the template provided in the Component Editor. Ensure you add all required signals (e.g., awaddr, wdata, bresp) and match the bus widths.

5) if I enable/configure SPI or Ethernet, is the C driver enabled in Eclipse? how to enable the driver?

• Install NIOS II EDS: Ensure you have the NIOS II Embedded Design Suite (EDS) installed.
• Create a New Project: In Eclipse, create a new NIOS II application project.
• Add Driver Support: Include the SPI or Ethernet driver in your project. You can find these drivers in the BSP (Board Support Package) settings.
• Enable Driver: Configure the BSP settings to enable the SPI or Ethernet driver. This will include the necessary headers and libraries in your project.

Hope this help.

[ZhiqiangLiang]

@JitLoonL_Altera 

Thank you for you reply!

1) I know how to add UART to NIOS. my question is: if I add a general/common UART, could I program/burn NIOS firmware(not FPGA bitstream) via the UART? If I would like to program/burn NIOS firmware(not FPGA bitstream), how to configure the UART or how to enable NIOS SDK?

2)  is there a way to program/burn NIOS firmware and FPGA bitsteam via JTAG or UART together? how to configure NIOS and how to enable it in SDK? Could you please tell me the detailed steps for JTAG and UART programming/burning and configuring method respectively?

3)  I didn't get your explanation about Check Resource Utilization. Could you please explain the detailed steps? and how to calculate the remained FPGA resource and RAM size I can set?

4) Your explanation about Conduit and AXI4Lite is very clear. I got it. Thank you.

5) I installed the software QuartusSetup-18.1.0.625-windows.exe whose size is 2272090KB. I don't know where the EDS is installed together. is there a way the check whether it is installed or no? By the way, I could open Eclipse  via Tools--> NIOS II Software Build Tools for Eclipse which is installed for embedded system.

[JitLoonL_Altera]

1. Programming/Burning NIOS Firmware via UART

To program or burn NIOS firmware (not the FPGA bitstream) via UART, you need to ensure that the UART is properly configured and that the NIOS II SDK is set up to use the UART for communication. Here are the general steps:

1. Add UART to NIOS II System:

   • In the Qsys (Platform Designer), add a UART component to your NIOS II system.
   • Connect the UART to the NIOS II processor and configure the UART settings (baud rate, data bits, parity, etc.).

2. Configure UART in NIOS II SDK:

   • In the NIOS II Software Build Tools for Eclipse, create a new NIOS II application project.
   • In the BSP (Board Support Package) settings, configure the UART as the standard input/output device.
   • Ensure that the UART driver is included in the BSP.

3. Programming via UART:

   • Use a terminal program (e.g., PuTTY, Tera Term) to connect to the UART.
   • Use the NIOS II command-line tools (e.g., nios2-terminal, nios2-download) to download and run the firmware via UART.

2. Programming/Burning NIOS Firmware and FPGA Bitstream via JTAG or UART

JTAG Programming:

1. Configure JTAG:

   • Connect the JTAG cable to the FPGA board.
   • In Quartus, open the Programmer tool.
   • Add the FPGA bitstream file (.sof) and the NIOS II firmware file (.elf).

2. Program FPGA and NIOS II:

   • Program the FPGA with the bitstream file.
   • Use the NIOS II command-line tools (e.g., nios2-configure-sof, nios2-download) to download the firmware to the NIOS II processor.

UART Programming:

1. Configure UART:

   • Follow the steps mentioned in the first section to add and configure UART.

2. Program via UART:

   • Use a terminal program to connect to the UART.
   • Use the NIOS II command-line tools to download and run the firmware via UART.

3. Checking Resource Utilization

To check resource utilization in Quartus:

1. Compile the Design:

   • Compile your design in Quartus.

2. View Resource Utilization:

   • After compilation, open the Compilation Report.
   • Navigate to the "Resource Utilization by Entity" section to see the usage of logic elements, memory, DSP blocks, etc.

3. Calculate Remaining Resources:

   • Subtract the used resources from the total available resources to determine the remaining resources.
   • For RAM size, check the "Memory Usage" section in the Compilation Report.

5. Checking EDS Installation

To check if the Embedded Design Suite (EDS) is installed:

1. Check Installed Programs:

   • Go to the Control Panel and check the list of installed programs for "Altera Embedded Design Suite" or "Intel FPGA Embedded Design Suite".

2. Open Eclipse:

   • If you can open Eclipse via Tools -> NIOS II Software Build Tools for Eclipse, it indicates that the EDS is installed.

3. Check Environment Variables:

   • Check if the environment variables (e.g., NIOS2EDS_ROOTDIR) are set correctly.

[ZhiqiangLiang]

@JitLoonL_Altera 

Thank you for your reply!

According to your explanation,  I have the following understanding, please help to tell me whether my understanding is correct or not:

1) UART for burning/programing is the same as a common UART. when I use burning tools to send firmware(elf)  via UART, the driver/bootloader in NIOS will get to know whether it is firmware or not, and will then save it at correct location in ROM/flash.

2) I can use both UART or JTAG interface to burn both firmware(elf) and bitstream(sof).

3)  I am using Quartus 18.1. In compilation report, I can see the total size of memory used, but I can't see the total memory available. For ROM, I have the same question.

4) in the following picture, Total PLL is 1. however, I didn't import PLL IP. why does it report 1 PLL used?

[JitLoonL_Altera]

Hi, 

1) UART for burning/programing is the same as a common UART. when I use burning tools to send firmware(elf)  via UART, the driver/bootloader in NIOS will get to know whether it is firmware or not, and will then save it at correct location in ROM/flash.

Yes, UART is just a standard serial interface — it doesn’t "know" the type of data. The ability to recognize firmware and write to flash comes from a bootloader that you must implement or include in your NIOS II system. By default, using nios2-download over UART loads the .elf to RAM, not Flash — it won’t persist after a reset.

To burn to flash via UART:

• You need a bootloader running on NIOS II that receives the data over UART and writes it to flash.

• Or use a prebuilt tool that supports flashing via UART (some vendors provide this).

Summary: UART works, but only if you have proper firmware on the device to handle the incoming data. It's not automatic.

2) I can use both UART or JTAG interface to burn both firmware(elf) and bitstream(sof).

JTAG can program:

FPGA bitstream (.sof)

NIOS II firmware (.elf)

UART can:

Transfer .elf into RAM (temporary execution only)

Not program .sof (bitstream) — this requires JTAG or a Flash device during power-up

Summary: You cannot program .sof via UART. Only firmware (and only if a bootloader is present).

3)  I am using Quartus 18.1. In compilation report, I can see the total size of memory used, but I can't see the total memory available.

For ROM, I have the same question.

Quartus shows how much memory your design uses, but not how much is available directly in the report.

To find total available memory:

• Look up the FPGA part number in the Intel FPGA datasheet

• Example: Cyclone IV E EP4CE10 has 414 Kbits (~51.75 KB) of total embedded memory (M9Ks)

For ROM, if you use on-chip memory as ROM:

• Its size is defined when you add the memory block in Platform Designer (Qsys).

• Check Qsys or system.h file to see exact size.

4) in the following picture, Total PLL is 1. however, I didn't import PLL IP. why does it report 1 PLL used?

Valid and common question

Quartus sometimes inserts a PLL automatically even if you didn’t manually add one.

Reasons:

• Clock source needs frequency conversion to meet timing

• NIOS II debug interface or clock crossing domains

• IP blocks internally require it (e.g., clocked video or SDRAM controller)

Summary: It's normal. Quartus uses PLL resources behind the scenes even if you didn’t explicitly configure a PLL.

[ZhiqiangLiang]

@JitLoonL_Altera 

Thank you！

1） If I run NIOS in Cyclone10,  is there a inside small bootloader in it? If there is not bootloader or similar tools in it, how can I burn firmware to it for the first time? as I know, there should be a very very small boot tool in MCU so that it can boot the bootloader. To my understanding the boot sequence should be:

very small boot tool in MCU --> bootloader --> OS or firmware.

Could you please help to explain the detailed boot sequence in NIOS?

How can it boot in the first time?

You mentioned "a prebuilt tool" that could program flash via UART, could you please tell the link of the tool?

If I download the tool, how to burn it to NIOS in FPGA for the first time?

2) I am using Cyclone 10 LP 10CL120. I cannot find the default inside RAM size data in the datasheet. perhaps, I didn't find the correct datasheet?

3) For ROM, I know how to add ROM to NIOS, but I don't know what the maximum size ROM I can  set.  how to check the maximum ROM size available?

4) according to your explanation above, if I would like to burn firmware to flash,  I need a bootloader to save the firmware from RAM to flash.  If I use ROM,  do I need a bootloader to save the firmware  from RAM to ROM?

5)  For PLL, as you explained, Quartus inserts a PLL automatically. my further questions are:

If I insert 1 PLL to covert the input cystal oscillate frequency to a certain frequency, will Quartus not insert it any longer? should I manually delete the PLL Quartus insert?

6) For Jtag programing, please see the following picture. I insert 1 JTAG, the question is:

what pins of the JTAG should be exported so that I can connect a Hardware simulator to the PCB board to program?

[JitLoonL_Altera]

Hi,  

To answer your question

1. NIOS II Boot Sequence and Programming for the First Time

Is there a boot ROM inside Cyclone 10?
No — unlike microcontrollers (MCUs), FPGAs like Cyclone 10 LP do not contain built-in ROM or bootloader. Everything, including your NIOS II CPU and its program, is part of the FPGA bitstream.

Boot Sequence Concept in NIOS:

The boot sequence in FPGA (with NIOS) is:
[FPGA configuration from Flash (e.g., EPCQ)] → [FPGA loads bitstream including NIOS + memory + bootloader] → [Bootloader runs from on-chip memory or external RAM] → [Loads firmware from Flash to RAM, starts application]

How to program it the first time?

1. Use Quartus Programmer + JTAG Cable.

2. You design a bitstream that includes NIOS + small memory + bootloader.

3. Program the FPGA or configuration flash (like EPCQ).

4. After configuration, the FPGA will include NIOS running your bootloader or program.

Prebuilt UART Bootloader Tool?

You might be referring to SBT (NIOS II Software Build Tools) provided by Intel. One example is:

• nios2-flash-programmer: used to program flash devices via NIOS.

• If you want to boot over UART, you can create a simple UART bootloader using HAL.

2. Cyclone 10 LP On-Chip RAM Size

Cyclone 10 LP does not have fixed "RAM" like a microcontroller. You add on-chip memory blocks manually in Platform Designer. However, the available amount depends on the number of M9K blocks in your FPGA.

• For 10CL120, the total available memory is 4320 Kbits, i.e., 540 KB of internal RAM (M9Ks).

• You can distribute this to your design however you want — for instruction memory, data memory, buffers, etc.

3. ROM Size in NIOS II

There’s no physical “ROM” — what you're calling ROM is on-chip memory initialized with code (like reset vector).

• The maximum ROM size = total available on-chip RAM (M9K blocks).

• In Quartus, use "Fitter Resource Usage Summary" after compilation to see how much is used and how much is left.

• Platform Designer shows estimated M9K usage per memory block.

4. If I Use ROM, Do I Need a Bootloader?

• If you’re using on-chip initialized memory as ROM, it contains the firmware directly.

• No bootloader is needed if the firmware fits and is placed directly in this ROM.

• However, if your firmware is large and stored in Flash (e.g., EPCQ), then a bootloader is needed to load the firmware from Flash to RAM at runtime.

5. PLL Handling in Quartus

• Yes, Quartus will add a PLL if needed, but it’s best to insert and configure your own PLL if you want control over clock frequency.

• If you add your own PLL and connect clocks properly, Quartus will not insert another.

• No need to delete Quartus-inserted PLLs — just manage it from Platform Designer or Quartus IP Catalog.

6. JTAG Pins for Programming

To connect an external JTAG programmer (like USB Blaster), you need to export these pins:

JTAG Signal	Cyclone Pin Name	Direction
TDI	TDI	In
TDO	TDO	Out
TCK	TCK	In
TMS	TMS	In
nTRST (optional)		In

• These must be routed to a JTAG header on your board.

• You can refer to Intel JTAG header layout (10-pin or 6-pin).

[ZhiqiangLiang]

@JitLoonL_Altera 

Thank you for your patient explanation!

1) For JTAG Programming, please refer to my picture below.

I didn't any pin which have the same name as you mentioned. Did I insert the wrong JTAG? or what should I do to insert the JTAG in Platform Designer?

2) For the IRQ column, should I change the digit number?  Could you please explain what those numbers mean?

[JitLoonL_Altera]

Hi, 

1) JTAG Programming

In Platform Designer (formerly Qsys), if you're using a NIOS II system, you typically do not need to manually add a JTAG interface block. Instead:

• The JTAG interface comes automatically when you add a NIOS II processor, and it is used via the JTAG UART or JTAG Debug Module (DM).

• If you're looking for physical JTAG pin connections (TCK, TMS, TDI, TDO), those are part of the FPGA hardware design, not something inserted via Platform Designer. You handle them in the top-level Verilog/VHDL design or via the Pin Planner in Quartus.

To check or export JTAG pins:

• Open the Quartus project’s top-level design file (e.g., top.v or top.qsf).

• Use Assignment Editor or Pin Planner to assign JTAG signals to the correct FPGA pins (these are often automatically assigned depending on your dev board).

2) IRQ Column:

In Platform Designer:

• The IRQ column (Interrupt Request) defines the interrupt priority or vector number when you connect a peripheral (like a timer or UART) to the NIOS II processor.

• The number you enter (e.g., 1, 2, 3, etc.) determines the interrupt number that peripheral will use.

Rules:

• Each IRQ number must be unique for each peripheral.

• Lower numbers can be treated as higher priority depending on your interrupt controller setup.

Do you need to change them?

• Yes, if you have multiple interrupt-generating components, assign each a unique IRQ number.

• If your system only has one interrupt source, then you may just use 0 or any number as needed.

[JitLoonL_Altera]

I understand you have many questions, and it's great that you're exploring the Nios II and FPGA ecosystem in detail. To help you more effectively, I’ve compiled a list of official documentation and resources that cover your topics thoroughly:

Intel Nios® II Processor Handbook
https://www.intel.com/content/www/us/en/docs/programmable/683127/latest/overview.html

Covers architecture, boot flow, interrupts, memory setup, and more.

Platform Designer (Qsys) User Guide
https://www.intel.com/content/www/us/en/docs/programmable/683092/latest/overview.html

How to build systems, assign IRQs, connect peripherals, etc.

Nios II Hardware Development Tutorial
https://www.intel.com/content/www/us/en/docs/programmable/683125/latest/introduction.html

Step-by-step project, JTAG UART, IRQ config, ROM/RAM settings.

Configuring Intel® FPGAs Using JTAG
https://www.intel.com/content/www/us/en/docs/programmable/683209/latest/jtag-interface.html

JTAG basics, pin names, hardware setup (TCK, TDI, TMS, TDO).

Embedded Booting Options on Intel® SoC FPGAs
https://www.intel.com/content/www/us/en/docs/programmable/683184/latest/overview.html

Explains boot ROM, bootloader, firmware loading process.

Cyclone 10 LP Device Handbook
https://www.intel.com/content/www/us/en/docs/programmable/683157/latest/cyclone-10-lp.html

For checking internal RAM sizes, flash options, and device-specific info.

These should give you a solid foundation and answer most of your current and future questions. I'd recommend going through them first, they’re very detailed and well-structured.

[ZhiqiangLiang]

@JitLoonL_Altera 

Many thanks for your help!

I will try what I asked in Quartus and then ask you if I encounter more issues.

If it is possible to have a meeting at which I can share my desktop for you to guide me, it will great helpful and efficient.

[ZhiqiangLiang]

@JitLoonL_Altera 

I am still facing questions when I create a NIOS in Platform Designer. I am not using Quartus 18.1.

1) when I insert NIOS II, the JTAG IP is not automatically inserted.

2) if I add a JTAG IP manually, I cannot decide which JTAG pins should be exported.

Please see the following picture:

[JitLoonL_Altera]

1) JTAG UART not inserted automatically

This is expected behavior in newer Quartus versions. The Nios II processor does not auto-insert the JTAG UART or the JTAG-to-Avalon bridge. You need to:

• Manually add the JTAG UART IP (for terminal I/O) or JTAG to Avalon Master Bridge (if needed for memory access during debug).

2) Exporting JTAG Pins

You do not export JTAG pins manually in Platform Designer — these are handled outside of Platform Designer in the top-level Quartus project.

So for clarification:

• jtag_uart_0 is not a physical JTAG interface — it's a virtual UART over the JTAG debug cable, so it doesn't need export.

• The real JTAG pins (TDI, TDO, TMS, TCK) are already handled by Quartus I/O assignments (you don’t add them in Platform Designer).

• You only export other peripheral interfaces (e.g., clk, reset, external memory), not JTAG pins.

Correct Setup Summary

To get NIOS II + JTAG UART working:

1. Add Nios II processor in Platform Designer.

2. Add JTAG UART IP manually.

3. Connect:

   • clk to system clock.

   • reset to system reset.

   • irq to Nios II's interrupt line (optional but recommended).

4. You do not need to export jtag_uart_0 — Quartus uses it automatically via USB Blaster.

5. After generating HDL, compile the project.

6. In Nios II SBT, you should see JTAG UART available for terminal connection.

I recommend referring to the following official Intel resources, which provide clear guidance on working with Platform Designer and Nios II systems. These documents should help clarify many of your questions and allow you to explore the design flow in more detail.

• Intel Quartus Prime Pro Edition User Guide: Platform Designer
  https://cdrdv2-public.intel.com/817606/ug-683609-817606.pdf

• Nios II Processor Reference Guide
  https://cdrdv2-public.intel.com/666887/n2cpu-nii5v1gen2-683836-666887.pdf

• Nios II Software Developer Handbook
  https://www.intel.com/programmable/technical-pdfs/683525.pdf

• Embedded Design Handbook
  https://www.intel.com/programmable/technical-pdfs/683689.pdf

Please go through these resources as they cover the fundamentals and should address most of the questions you've raised.

[ZhiqiangLiang]

Dear@JitLoonL_Altera 

I am now doing the following:
1) add NIOS II.

2) add UART which is used to communicate with outside MCU.

3) add SPI_ADC which  is used to initialize ADC.

4) add SPI_Freq which is used to initialize frequency mixture.

5) add JTAG_UART which is used to program/burn bitstream(sof) and firmware(elf).

6) set NIOS vectors page as ROM.s1 and RAM.s1.

My questions are:

--> are my upper settings correct?

--> For JTAG, it is not added by Platform Designer automatically, but added by me manually. Did I add it correctly? how to export JTAG_UART's pins?

The generate nios_core interface is shown in the following picture from which we see that there is not JTAG pins exported.

[JitLoonL_Altera]

Additional info.

When you don’t need to export JTAG pins:

• Standard Nios II and JTAG UART flow: If you are using the Nios II processor along with the JTAG UART IP (used for communication between the host and the processor), you don’t need to export physical JTAG pins.

• The JTAG interface (TCK/TDI/TDO/TMS) is already available and accessed directly through the FPGA’s built-in JTAG port, which is already on your development board.

• Toolchain like Quartus and the programmer tool automatically uses these JTAG ports without requiring you to manually export them.

Examples of when no export is needed:

• Using Nios II Debug Interface with JTAG UART in your Platform Designer.

• Working with the built-in JTAG interface for debugging and programming.

 

When you need to export JTAG pins:

• Custom or special JTAG interface: If you are designing a custom JTAG interface (for instance, creating your own soft JTAG in your IP), then you will need to manually export the JTAG-related pins.

• If your design requires a unique or non-standard JTAG setup (outside the typical Nios II + JTAG UART setup), this will require exporting the JTAG pins from Platform Designer.

Examples of when export is needed:

• Designing your own custom JTAG interface.

• Implementing a soft JTAG in your IP that requires dedicated pins for TDI, TDO, TMS, and TCK.

[ZhiqiangLiang]

@JitLoonL_Altera 

Thank you for you patient reply!

I still have 2 more questions about JTAG:

according to your explanation above, in FPGA, JTAG ports are automatically connected to FPGA hardware pins.  what pins  of FPGA are  connected built-in JTAG ports?

The most detailed datasheet I can find is at: https://www.intel.com/content/www/us/en/docs/programmable/683251/current/document-revision-history-for-the-device.html

Do you have more detailed datasheet which tells me what FPGA pins are used for JTAG?

[SueC_Altera]

Hi ZhiqiangLiang,

You can find the device pin outs here.

Sue

[ZhiqiangLiang]

@SueC_Altera 

Thank you!  Your link helps.

[ZhiqiangLiang]

I set RAM == 122880B, and ROM==81920B.

The question is:

I cannot set RAM + ROM = 540KB which you told me in this thread.

Even if I slight reduce RAM + ROM which is slight smaller than 540KB, I still encounter the size too big issue.

[ZhiqiangLiang]

@JitLoonL_Altera 

Thank you for help!

I now can add NIOS and related interface in Platform Designer, and I am also able to build firmware in Eclipse successfully.

I get a new question:
I would like add a new GPIO to NIOS so that I can control the GPIO in C code to light the LED that is connected to FPGA pin. how to add  GPIO to NIOS in Platform Designer? how to control the GPIO in C code?  how to access those interface in C code? is there any example C code for reference?