Creating a Ibex component in platform designer on Arria 10 FPGA development board

[Nikitha_Sree]

Hello Everyone, 

I'am trying to create an Ibex component in the platform designer and trying to connect JTAG UART IP, On chip memory IP to that 

am facing the below connection errors : 

Error: riscvcomp: Connection (post-transform) is missing an end point: riscvcomp_myriscv.dm_axi4_master->null
Error: riscvcomp: Connection (post-transform) is missing an end point: riscvcomp_myriscv.im_axi4_master->null
Error: riscvcomp: Connection (post-transform) is missing an end point: clock_in.out_clk->null
Error: riscvcomp: Connection (post-transform) is missing an end point: clock_in.out_clk->null
Error: riscvcomp: Connection (post-transform) is missing a start point: null->riscvcomp_jtag_uart.avalon_jtag_slave
Error: riscvcomp: Connection (post-transform) is missing a start point: null->riscvcomp_pio.s1
Error: riscvcomp: Connection (post-transform) is missing a start point: null->riscvcomp_intel_onchip_memorry.s1
Error: Internal Error: Cannot generate a system with dangling connections.

Please find the attached screenshot for reference. 

Can anyone please provide how to resolve this issue

thanks in advance . 

[TingJiangT_Intel]

Could you please help upload a design example for further investigate on this? Thanks

[Nikitha_Sree]

Hi TingJiangT , 

I developed a component (myriscv) with the AXI4 Manager bus for Instruction & Data Manager and internally assigned to clock, reset, and this is the master. When I try to connect to the JTAG UART IP and on chip memory IP as slaves, I got the following issues:

Error: riscvcomp: Connection (post-transform) is missing an end point: riscvcomp_myriscv.dm_axi4_master->null
Error: riscvcomp: Connection (post-transform) is missing an end point: riscvcomp_myriscv.im_axi4_master->null
Error: riscvcomp: Connection (post-transform) is missing an end point: clock_in.out_clk->null
Error: riscvcomp: Connection (post-transform) is missing an end point: clock_in.out_clk->null
Error: riscvcomp: Connection (post-transform) is missing a start point: null->riscvcomp_jtag_uart.avalon_jtag_slave
Error: riscvcomp: Connection (post-transform) is missing a start point: null->riscvcomp_intel_onchip_memorry.s1
Error: Internal Error: Cannot generate a system with dangling connections.

Please look the screenshot attached for the reference. 

Please suggest the needful to be done. 

Thanks,

Nikitha  

[TingJiangT_Intel]

Hi there, Please try to click the 'Remove Dangling Connections' option under the 'System' and see if it can be solved:

​

[Nikitha_Sree]

Hi TingJiangT ,

Thanks for the response. 

Under the System --> Remove Dangling Connections is not been highlighted for selecting. 

Please find the screenshot for reference.  

Can you give me some information regarding the timer_sw_agent ,dm_agent in the Nios V Processor IP and there signals. 

Thanks 

Nikitha

[yanlalalala]

Hi Nikitha,

According to your snapshot, you are using a custom component called myriscv as the soft processor right? I'm sorry to say that we cannot automatically remove dangling connections for custom components.

If you want to modify your component refer to Nios V Processor, you can use this user guide 4. Nios® V/g Processor (intel.com)
All information we can provide are included in this ug.

Thanks,

Ivy

[TingJiangT_Intel]

Hi there, any updates on this issue?

[Ranjani]

HI @TingJiangT_Intel ,

I am at the same point where Nikitha sree is. I am able to build the qsys environment. When I try to create bsp file to export to Ashling I am stuck at this point. Ibex is not listed in dropdown. please help me with this.

Regards

Ranjani