Custom Instruction addition

[Altera_Forum]

Dear all 

 For making the New component for custom instruction addition to Nios processor Five tabs are to be completed    new system component,    1)introduction, 2)hdl files, 3)signals, 4)interfaces, 5)component wizard   After completing first 4 tabs    In the component wizard(5th) tab   In the parameters box it displays (no top level verilog/vhdl parameters)    I did as suggested in this link   http://blog.ednchina.com/chactor/28614/category.aspx   (please click translate button in the top to convert it to english)   But in the link given above shows in Component wizard tab in parameters box displays(5th image from top)   CRC_width, polynomial_ntal, polynomial, reflected_input in the Parameters    Why it is happening for me that when i make it my parameters in component wizard tab is empty   Please clear my doubt    Regards M Kalyansrinivas

[Altera_Forum]

Could you show us the code of your top level VHDL/Verilog file for the custom instruction?

[Altera_Forum]

Hi  

The code is direct as i just took the template of Multicycle logic code  given in quartusII installation directory    and added a simple direct logic to it      // Verilog Custom Instruction Template File for Multi-cycle Logic module custominstruction( clk, // CPU system clock (always required) reset, // CPU master asynchronous active high reset (always required) clk_en, // Clock-qualifier (always required) start, // Active high signal used to specify that inputs are valid (always required) done, // Active high signal used to notify the CPU that result is valid (required for variable multi-cycle) dataa, // Operand A (always required) datab, // Operand B (optional) result // result (always required) );   //INPUTS input clk; input reset; input clk_en; input start; input [31:0] dataa; input [31:0] datab; //OUTPUTS output done; output [31:0] result; reg [31:0] temp; reg[31:0] result; // custom instruction logic (note: external interfaces can be used as well) always@(posedge clk,posedge reset) begin if(reset) result <= 32'b0; else if(clk_en) begin if(start) temp <= dataa+datab; else if(done) result <= temp;  end  end endmodule   regards M Kalyansrinivas

[Altera_Forum]

Your code doesn't have parameters (I don't know the exact equivalent of "generics" in Verilog) and that's why your parameters list is empty in the component wivard. 

In the example shown on the page you linked, the code they used had multiple parameters, and that's why they appeared on the list.  Having an empty list in your case is perfectly normal, you can carry on and create your custom instruction.  Edit: I never made any custom instruction, but I find it strange that you never set the value of the 'done' output. Instead you seem to be using it as an input...

[Altera_Forum]

Hi Daixiwen  

 Thanks alot for clearing my doubt    Ok i will correct the verilog code as you said    I have made it according to the procedure defined but i see the multi cycle ports (start,done,clk_en) doesnt appear in the macro generated in the System.h file    As they are defined as inputs and outputs they should appear in the macro   Please help me out    A similar problem is reported by some other friend keitall   http://alteraforums.com/forum/showthread.php?t=20044   Regards M Kalyansrinivas

[Altera_Forum]

Those signals are automatically generated by the CPU, you don't need to control them through the macro. 

The only arguments you should see in the macro are the instruction operands, and of course the result.

[Altera_Forum]

Thankyou very much for the reply  

 I will try out some examples   Thankyou once again   regards M Kalyansrinivas