Custom component writing to SD-RAM

[Altera_Forum]

Hi fellows, 

 i have created a system in which nios II processor is running at 100 MHZ and ddr sdram is running at 150 mhz so , i also added a clock crossing bridge,   after this i created a custom slave component which is perfectly accepting what is coming from nios II. But i need by custom slave component to write to sdram?  what is the best way to do it?  and please show example designs if possible..  thanks for your help...

[Altera_Forum]

One more thing i forgot to mention, this slave should also be able to receive data from sdram.  

 now the question is more complete.   looking forward to your helps....

[Altera_Forum]

You can add an Avalon master port to your custom component. Through this master port, you can write to and read from your SDRAM (or any other slave component). Components can contain more than one Avalon port including a mixture of both master and slave ports.

[Altera_Forum]

is there an example where an custom avalon master writing to sdram?

[Altera_Forum]

Perhaps one of the master examples on the altera website (http://www.altera.com/support/examples/nios2/exm-avalon-mm.html) would be useful?  

 One thing to keep in mind is that you really shouldn't be too worried specifically about how to write to SDRAM but instead how to write to an Avalon slave. Writing to any slave, including SDRAM, is the same.  Another thing to watch out for is that SDRAM is an example of a high latency slave, particularly for reads. Because of this, if you need to achieve high bandwidth/efficiency to the slave, you will need to use pipelining or burst transfers.

[Altera_Forum]

Here are some other examples written in VHDL: http://www.alteraforum.com/forum/showthread.php?t=19053 

 The master templates up on the altera design examples page are an early version of what is used here: http://www.altera.com/support/examples/nios2/exm-modular-scatter-gather-dma.html This one is more feature rich and uses standard streaming interfaces for the control, response, and data plane interfaces so I would recommend it over the old templates.  When accessing SDRAM in general make sure you study the master access pattern. Accessing locations sequentially will give you the best performance and random accesses all over the place will give you the least performance (in general).