Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
12615 Discussions

Cyclone V FPGA-to-HPS Bridges design example bug?

Altera_Forum
Honored Contributor II
1,163 Views

I found what appears to be a bug in the example_design.c file, but didn't see a means to report it directly. So, I'm posting it here. 

 

example_design.c:233 

 

for(int i=0; i<test_set->hardware_instances; i++) { test_set->bg_counters = 0; }  

 

should be 

 

 

 

for(int i=0; i<test_set->hardware_instances; i++) { test_set->bg_counters = 0; }  

 

 

(see https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html)
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
411 Views

Hi, 

 

Thanks for notifying the bug, let us check/workaround it. 

We will get back to you on this as soon as possible. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
0 Kudos
Reply