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Downloading ELF Process failed Arria V GX Starter Kit

Honored Contributor II



I am currently receiving errors regarding downloading the ELF process to my Arria V GX starter kit. Basically what I am trying to do is complete the nichestack tutorial (for cyclone III, V and Stratix IV devices) on the Arria V GX starter kit. I have used the Qsys files supplied for these other boards to form my own Qsys system, and have created the needed VHDL code for my project. I am also using the same exact nichestack files provided with the Cyclone III 3C25 board for the tutorial (I believe the .c files should remain the same, right?) My code compiles in Quartus II, and when I go through the nichestack tutorial steps, the project in eclipse also builds successfully, generating a .elf file. However, I obtain errors while trying to download the .elf process to the board after running as Nios II Hardware. Basically I get an error that downloading the ELF process failed, and also an error that states:  


assertion "m_state == STATE_DEBUG: failed: file "nios2debug.cpp", line 578 /cygdrive/c/altera/12.1sp1/nios2eds/bin/nios2-download: line 609 9372 aborted 


I have done much searching around on the forums for a solution, and I have even sought out help from fellow colleagues. If you could offer any kind of advice or solution it would be greatly appreciated. Again I am simply trying to convert the given QSYS and VHDL ethernet files given on the altera website to be compatible with the Arria V GX starter kit. Maybe there is a certain device given that is very similar to the Arria V? I have the correct pins assigned in the pin planner, and have modified essentially the cyclone V's QSYS files to match the specs of the Arria V (memory size, ethernet type, pin outs, etc.) I am fairly new to using QSYS and Eclipse, although I have a pretty good background of Quartus II and VHDL language. I feel that as long as the code compiles and builds, there should be no problems in downloading it to the board. The .sof file from Quartus downloads fine to the board, it is just the .elf file that I cannot seem to crack. It has stumped me for a couple of days now, so any advice is greatly appreciated. Thank you very much for your time. 





Arria V GX Starter kit (FPGA: 5AGXFB3H4F35C4N) 

Quartus II Version 12.1 SP1
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Honored Contributor II

When you program in NiosII, in the BSP setting-> BSP editor -> linker script-> change the memory from ddr/sdram to onchip mem. 


The problem would get solved
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