EPCS fpga+nios field update

[Altera_Forum]

Hi,  

 I know this has been asked several times, but I can't seem to find an answer that fits my problem so here it goes:    I have a large CIII design with a NIOS including the remote update block.  What I would like to do is to load a new firmware (hw+sw) from an SD card and flash it to the epcs and the restart the system.    So far I have used the an429 example from which i have fittet the parser and programmer to my design. I THINK that the flashing but when the system is restartet my board i dead.    This leaves me with several questions :confused: :   1. Which files from should I used to flash the epcs? right now im using the hw.flash generated from the sof and the epcs0.flash for the nios.    2. How to i now from which address I should boot?    3. am I missing something else? :eek:    thanks!    greetings,   mitch

[Altera_Forum]

The application selector design example for the NEEK has pretty much everything you need...altremote_update, copy from SD card, remote configuration. 

 The example is available on Altera's website....here (http://www.altera.com/support/examples/nios2/exm-demo-loader.html). If I were you, I'd pay particular attention to the methods used in software.  Cheers,  - Brendan

[Altera_Forum]

Just to gain some clarity here: 

 1 - The FPGA will always attempt to load an image starting at address 0 of the EPCS flash unless you've specifically given a different address using the altremote_update core. 2 - The default bootloader for the NIOS when booting from the EPCS will automatically look at the FPGA image, then skip to the end of the file and expect to find the beginning of your software code there.  So here is the question. Are you simply going to overwrite your existing image and software in the EPCS flash or are you planning on keeping a safe image that you'll never overwrite?  You may want to refer to this post: http://www.alteraforum.com/forum/showthread.php?t=5244&referrerid=2226  In any case, the data you want is the raw binary FPGA image data and the binary software data. Here is a script I have given before to produce the binary files (note that in my script I append the software to the FPGA image to create one single file): # Creating .flash file for the FPGA configuration echo Creating firmware flash file ... "$SOPC_KIT_NIOS2/bin/sof2flash" --epcs --compress --input="../altera/top.sof" --output="firmware.flash" # Creating .flash file for software code echo Creating safe and application flash files ... "$SOPC_KIT_NIOS2/bin/elf2flash" --epcs --after="firmware.flash" --input="../software/top/Release/top.elf" --output="app.flash" # Convert to binary echo Converting flash files to binary ... nios2-elf-objcopy -I srec -O binary firmware.flash firmware.bin nios2-elf-objcopy -I srec -O binary app.flash app.bin # Concatenate echo Concatenating binary files to create final programming file ... cat firmware.bin app.bin > app_image.bin  Jake

[Altera_Forum]

I want to keep a safe image that should never be erased.  

 When my factory image fpga+nios is placed at 0x0 in the EPCS, how do I make sure that the user image is placed somewhere else?    Do I need a modified boot loader when I'm using the remote update controller to change the boot address?     - mitch

[Altera_Forum]

What I have done so far is: 

 1. generate a combined flash file in the format sof followed by elf  - offset is 0x000e0000 2. read the file and program the EPCS with the an429 programming routines 3. change the hw offset in the remote update component to 0x000e0000 4. restart      unfortunately my factory image is still loaded (prgrammed at 0x0 with the flash programmer)    What am I missing?

[Altera_Forum]

Let me explain how this works. By the way yes you do have to write a custom bootloader. 

 1 - You power-up the board. 2 - The FPGA begins active serial configuration and programs itself using the FPGA image stored at address 0x0 of the EPCS flash. 3 - Once the FPGA is programmed, the NIOS processor starts up and boots from an onchip RAM block located inside the EPCS flash controller component in your SoPC builder system. This is the bootloader. The source code for this bootloader can be found in your altera install directory: C:\altera\91\nios2eds\components\altera_nios2\boot_loader_sources 4 - The bootloader mentioned above looks at the FPGA image located at address 0x0 and determines how long the image is. 5 - The bootloader jumps to the end of the FPGA image where it expects to find the software image (ELF). 6 - The bootloader copies the software image to RAM and then executes a non-returnable jump to RAM to start your program running.  So what you need to do is create a modified bootloader that will intervene in this process after step 2. Your bootloader needs to:  1 - Determine which FPGA image just got loaded (application or factory). 2 - Decide what to do next. If the current running FPGA image is the factory image you can: . a) stay in factory mode and load a factory software image. . or . b) use the remote update core to attempt to load the application image  3 - If the current running FPGA image is the application image then it stands to reason that you will want to load the application software.  It's unfortunate the the NIOS forum crashed some time ago as all this information has been detailed in the past.  Jake

[Altera_Forum]

hmmm sounds quite complicated!?  

 If I wanted to just have one image that gets overwritten which files should I use?   -mitch

[Altera_Forum]

It's really not that bad. I can give you my modified bootloader if you want it but it's been hand-tweaked for my design and Stratix II GX. You could also post a new topic asking if anyone has a modified bootloader that they're willing to share. 

 But if you just want to have one image, I suggest using the script I've given above. This will create a single file that contains both your SOF and ELF files. Then you just program this file starting at address 0x0 in the flash.  Jake

[Altera_Forum]

That would be great if I could have a look at your boot loader :D  

That way I could get an idea of how it is done, and maybe adapt one myself:confused:   -mitch

[Altera_Forum]

Here you go. I don't have a lot of time to explain all the details. Remember this one is customized for Stratix II GX. Your best bet to see what I've done is to diff these files with the ones in the original Altera install. 

 Feel free to ask any questions.  Jake

[Altera_Forum]

Thanks :D  

 I will give it a shot!   -mitch

[Altera_Forum]

okay so I managed to create a boot loader based on yours which holds 

 safe image at 0x0000 page 0x0 user image at 0xe0000 page 0x0    My question is now; how do I get it into my design flow in order to create the base image with the safe image?    I did the following:   'elf2flash --after=factory.flash --epcs --input=sw.elf --output=sw.flash --boot=fos_boot_loader_epcs.srec'    which I programmed into the epcs, the factory firmware was loaded correctly!    then I made the user firmware by:   ' bin2flash --input=app_image.bin --output=app_image_flash --location=0xe0000'    and programmed it to the epcs    When I run the reconfiguration my factory fimrware is still loaded!   -mitch

[Altera_Forum]

I'm a little surprised that you created the bootloader so quickly. Makes me wonder if you missed something. Let's assume you didn't though. 

 By default, the EPCS controller peripheral in the SoPC system contains a block RAM. This block RAM contains the bootloader. That is why setting your NIOS processor's reset address to the address of the EPCS controller works.  That bootloader that I wrote is meant to replace the bootloader that is inside the RAM in the EPCS controller peripheral. If you are going to do it the same way you need to find some way to get your compiled bootloader into that RAM in place of the default bootloader.  I'm going to suggest a way of doing this that I actually haven't done yet but I think it will be easier for you.  Look in the folder where you've generated your SoPC system. You should see a file named something like "epcs_controller_boot_rom.hex". Your name might be different if you named your EPCS controller component differently. That ".hex" file contains the compiled bootloader that goes into the RAM block. Quartus compiles it into the FPGA image during assembly. You need to overwrite that file with your own compiled bootloader.  1 - Compile your bootloader. 2 - Create a .hex file (or .mif) file out of your .elf file and name it the same as the one being used by the EPCS controller. 3 - Copy your ".hex" file over the top of the old one. 4 - From Quartus run "Processing->Update Memory Initialization File". When that completes run "Processing->Start->Start Assembler". (If you have Smart Compilation enabled for the project you should just be able to hit the compile button and it will automatically determine just to do these steps). This will create a new SOF file with your bootloader in the EPCS RAM block.  You'll need to keep an eye out to see if/when your bootloader gets squashed by the other one (I assume it's going to be regenerated at some point). If you want to avoid this, I can suggest another method that may be slightly more complicated. It's basically telling Quartus to use a different ".hex" file to initialize that RAM block instead of the original.  Jake

[Altera_Forum]

thanks, will have to try that tomorrow :) 

 What I did was to compare your files agains the standard ones in my altera installation.  Since the standard ones are made for the stratix as well as the cyclone I assumed that I just needed to add your check routines for the safe and the user image to my file. Uncomment the altera standard ID checking.  And then run a make together with my system.h and epcs base.  This is properly not the most elegant way :rolleyes:   -mitch

[Altera_Forum]

The other part you're going to have to change is my code that interacts with the remote update controller. This is not the same for Cyclone III. 

 Jake

[Altera_Forum]

So it is not enough too point it to he EPCS base address and make sure that the compared registers are those written by the remote_update block? 

 -mitch

[Altera_Forum]

Hi Jake, 

 I´m also trying to use the remote system upgrade, changing the boot. I´ve already seen other posts from you about this issue, hope you can help me. I can´t manage to build the boot (not even the altera original files without any change).  I´m just taking the sources in: C:\altera\90\nios2eds\components\altera_nios2\boot_loader_sources  Without any change, and within this folder, I´m trying with the command shell: make CODE_BASE=0x000000 EPCS_REGS_BASE=0x2001800 clean all  (in the SOPC the epcs controller is on base address from 0x2001800 to 0x2001fff)  Next, I type: elf2hex --base=0 --end=0x1ff --width=32 --input=obj/boot_loader_epcs_sii_siii_ciii.elf --output=epcs_flash_controller_0_boot_rom.hex  The output file has the same name as the default (epcs_flash_controller_0_boot_rom.hex). Thus, the INIT memory of the EPCS has the file already assigned, and I only overwrite it in the quartus folder.  I recompile the quartus project, and I use the flash programmer to program the, the sof+application. After power down, It doesn´t boot anymore.  1- Am I using the elf2hex properly? what about the --width and --end? 2- My device is EP3C40, am I using the correct file or shall I use any other of the altera "boot_loader_sources" folder? I tried "boot_loader_epcs_sii_siii_ciii_be.elf" and "boot_loader_epcs.elf", but it´s the same.  I started this with Quartus 9.1 64 bits, but I changed to Quartus 9.0 32 bits, as I thought that there may be some bugs...(have no idea what else to do).  Thanks in advance, Melo

[Altera_Forum]

I have found some nice example here: http://www.grigaitis.eu/?p=514  

There is remote update example to EPCS using UART it may help...

[Altera_Forum]

Hi Melo, 

 did you find the solution in the meantime? I've got the same problem...

[Altera_Forum]

Hi, 

yes, I finally did it. from the source code of the boot of altera and the one of "jakobjones", withing the folder of the makefile, just type in the command shell: "make clean all".  The makefile includes in the INCLUDES2 the folder where the system.h is, to take the BASE of the remote_system_upgrade. From the files I took from "jakobjones", I changed the boot_loader.S and the boot_loader_epcs_bits_sii_siii_ciii.S. For example, when it reopens the epcs at byte_N, I do:   addi r_flash_ptr, r_reconfig_image_base, N   I read the remote system upgrade, and boot from the address 0x200000 if the reconfiguration register is not zero. Finally, I create the .hex with:  elf2hex --width=32 --base=0x0 --end=0x3ff --input=obj/boot_loader_epcs.elf --output=epcs_flash_controller_0_boot_rom.hex --record=4 --lower  It works. Remember you have to do it again everytime you make a generate in the sopc, as it overwrites the file with the standard "epcs_flash_controller_0_boot_rom".  I've attached the makefile, boot_loader.h, boot_loader.S and boot_loader_epcs_bits_sii_siii_ciii.S. (sorry, I don´t have the winzip at this moment, I just added the .doc extension to upload the file, just throw it).  hope it helps, Melo.

[Altera_Forum]

I have a Cyclone III (3C16) with a NiosII processor with external RAM and I would like to have remote update functionality. My first goal is to able to switch from safe image to user image for as the FPGA configuration (hardware image) and NiosII executable (software image)... and I cannot get this workign! 

I'm able to have a safe and user hardware as wel software image in the EPCS device for my Cyclone III I'm using the Remote System Update and I'm able to switch from the first hardware image to the second hardware image.  But the problem is that my second hardware image loads the software image of my first hardware image.  So after reading several threads on the forum and AN458, AN429 and AN548 I understand that I need to change the bootloader of the EPCS controller. I should give an offset where the bootloader is going to search for the NiosII software Image.  The content of the EPCS is as follow: 0x00000 hwimage_app1..hex followed by swimage_app1.hex 0x90000 hwimage_app2.hex followed by swimage_app2.hex   I'm not very experienced in assembler... but I tried the file "boot_loader_epcs_bits_sii_siii_ciii.S":  // 1) Open EPCS-device at flash-offset zero.  //  movi r_flash_ptr, 0 and changed it to "movi r_flash_ptr, 0x90000". Then I compiled these files with the make command in the boot_loader_sources directory, I replaced my EPCS_controller in the SOPC builder, generate the NiosII and recompile the Quartus project.   I also checked the bootloader from Melo_01.. and from his comment in the sources I understood that he is spanish...    Can any one help me to change the bootloader to start my second software image. I think I only need to make a small step...