Error: Connected system ID hash not found on target at expected base address

[Altera_Forum]

Hello, 

 Usual sentence first: I'm fairly new to FPGA programming, so bear with me.  I tried to follow the Nios II Hardware Development Tutorial (version 3.0, Dec. 2009) using the latest (v 11.0) tools (Quartus II, Nios II Tools etc.) on Windows 7.  Everything works relatively smoothly (only problem is a timing issue with the JTAG, which I can't solve but can be ignored if I understand correctly). The .sof is written onto the FPGA. It consists of a cpu, onchip_mem, sysid, led_pio (it's a Cyclone III eval board), sys_clk_timer and a jtag uart.  The tutorial uses the count_binary sample and everything compiles without error. However, if I try to do Run As -> Nios II Hardware a windows pops open telling me "connected system id hash not found on target at expected base address."  If I click System ID Properties I get: Expected system ID base address: 0x11030 (which is the one in the SOPC builder) Expected system ID: 0x0 (which is the one in the SOPC builder) connected system id: not found Expected system timestamp: 1306314921 connected system timestamp: not found  I can see the connected USB-Blaster in the Processors and Byte Stream Devices panel.  Any suggestions would be much appreciated  U.

[Altera_Forum]

--- Quote Start ---  Since you failed to get the systemID and timestamp, a quite simple thing to complete, there is something wrong with the cpu and memory system. I just figure out the same problem as you have. Here is my experience for reference.  I checked my design carefully and found nothing doubtful, so I wondered why the cpu didn't respond to the PC. Oh, I forgot the reset signal and it was asserted forever by a switch. I flipped the switch and every thing worked.  So, figure out why your cpu doesn't respond the systemID inquiry, then you can advance to the next step.  --- Quote End ---     yeah,I encountered this problem two weeks ago, today I figure it out , there is sth wrong with my reset setting, I FORGOT to assert a right reset button

[Altera_Forum]

--- Quote Start ---  yeah,I encountered this problem two weeks ago, today I figure it out , there is sth wrong with my reset setting, I FORGOT to assert a right reset button  --- Quote End ---    I am also getting the same error. I am using a quartus design with sdram. Which reset setting to be changed? How can I change the reset setting?

[Altera_Forum]

I fixed this problem on my machine. The tutorial files worked, but if I modified enough things from them, the FPGA would not program right. I ended up deleting all of the altera settings folders located in my home directory (C:\users\<username>) and restarting the program letting quartus recreate the folder from default. It seems to have evened out the missing ID problem for me.

[Altera_Forum]

I got the same problem when using Quartus II 12.0 with Altera UniPHY IP. 

For my case, the error is introduced by the input clock for sysid module that connects to UniPHY afi_half_clk. As reported in following thread, afi_half_clk from UniPHY is stuck to 0.  DDR2 SDRAM with UniPHY not generating half_rate_clock: http://www.alteraforum.com/forum/showthread.php?t=39884

[Altera_Forum]

I disconnected the JTAG debug module reset in Qsys from the CPU and the other peripherals to get my Modelsim simulation working.  

 I had to reconnect the JTAG debug module reset to the CPU and all peripherals, except the clock source, to get the debugger working as I was getting this message.

[Altera_Forum]

Although this thread is very old. But I am just posting one of my experiences here, so that people may be befitted with it. Here are some possible fixes for this situation. 

 When system ID is not detected or timestamp, it is possible that some of irq signal from any peripheral is not connected in qsys, If so, connect all required irq signals and then regenerate the system. Update new .qip file in the project. And then use the generated schematic or hdl files.  Second problem may be connections in Schematic. Make sure that all the ports are connected to module. Look for any X(cross) symbol at the end of the connecting lines.   Thirdly, about elf downloading fail: When ever a new Qsys system is generated, regenerate bsp. Then in application project Index -> regenerate. Then Build project, and then run.

[falconar]

I had this same issue. My problem was that the pin configuration was wrong (specifically I had detailed extra switches that were not on my board). Ensure that all of the pins that are accessed by the Nios programmer are available as inputs/outputs and that they are connected to the correct pins in the .qsf file.