External Ram doesn't show up in NIOS cpu settings

[Altera_Forum]

Hi All, 

 I wanted to interface NIOS with a Cypress Static RAM instead of using the usual IDT RAM (which is present on the NIOS development board). I created a new component and specified avalon tri-state bridge in Interface section. My idea was that if I bring out all the signals of the tristate bridge out of the system, I will connect them (after taking them out to the FPGA pins) to my RAM signals. I didnot add any HDL entity. After adding this component to my system, I want to set Exception Address to this RAM. However this component is not available in the drop-down list against the Exception Address control.  Plz. guide me what I have missed in specifying the new component which could have made SOPC builder recognize that it is an external memory; so that it occurrs as an options in "NIOS cpu Settings" page.

[Altera_Forum]

Hello, 

 My first guess would be that when you created the interface to user logic, you chose "register slave" (or something like that), rather than "memory slave" -- this setting sets a value which the tools look at to determine whether your interface is a memory device that can be used for code, data, exceptions, etc.

[Altera_Forum]

What is the answer to this question, I have the exact same problem

[Altera_Forum]

Have you correctly added the static ram to the sopc definition? 

The cpu data master needs to be given access to the sram area.

[Altera_Forum]

not sure exactly what you are saying, can you explain further... 

 thanks