External Slave reset/clk signals

[Altera_Forum]

Hi all, 

 My typical method of interfacing my Nios/SOPC system with the rest of the logic on the FPGA is to create implement one or more avalon slaves outside of the SOPC module, and to add external slave ports to SOPC. To do this, I create an SOPC component with no HDL files, and whatever type of interface (address width, data width, etc.) I intend to connect. This works OK, but one issue is that "clock" interfaces do not get routed to external ports. Even when I create a clock or reset signal belonging to the clock interface, no external ports are created in the SOPC_System module.   I can connect them to the same reset that I supply to the SOPC_System, but the real problem comes from the fact that I have a DDR2 controller in the SOPC system, and I need to assert the reset to other modules outside SOPC until the SDRAM PLL is locked. The SDRAM controller has a reset_request output, but this does not seem to be accessible outside of the SOPC system.   Any ideas? Has anyone else faced this issue? Is there a reason that clock port signals are not made external?   Thanks,  -Jeff

[Altera_Forum]

Someone asked me about this the other day as well. This sounds like a bug but if you create a component that contains a file that wires the clk/reset and slave ports to a conduit that should work around the issue you are seeing. So you would just need a conduit containing signals that are in the opposite direction as the internal ports and just wire them together. 

 The DDR SDRAM controller connects it's I/O through a conduit just like what I'm suggesting above (except the component contains more than just wires).