Flip-flop by using logic gates

[Altera_Forum]

hi 

 I am a new to VHDL and currently doing VHDL assignment. In this assignment, required to create the D, JK flip-flop.   I need help to solve my error for my code as shown as below:   library ieee; use ieee.std_logic_1164.all;  library work;  entity Lab1 is   port ( J :in std_logic; K :in std_logic; clk :in std_logic; Q : out std_logic; qn :out std_logic );  end Lab1;  architecture arc of Lab1 is  signal W1 : std_logic; signal W2 : std_logic; signal W3 : std_logic; signal W4 : std_logic; signal W5 : std_logic; signal W6 : std_logic;  begin  qn <= W4; W1 <= not (J and clk and W4);  W2 <= not (K and clk and W3);  W3 <= W1 nand W4; W4 <= W2 nand W3;  process(clk) begin  if rising_edge(clk)then  Q <=(J and (not Q)) or ((not K) and Q);  qn <=not Q ;  end if; end process;  end arc; ------------------------------------------  Error (10309): VHDL Interface Declaration error in Lab1.vhd(41): interface object "Q" of mode out cannot be read. Change object mode to buffer.  Pls help me to solve the syntax error   Thanks

[Altera_Forum]

Two options: 

- change Q from out to buffer - use an internal signal Qi and copy it to Q outside the edge sensitive condition.  Also the assignment for qn must be placed outside the rising_edge() condition, otherwise it's delayed by one clock.

[Altera_Forum]

Hi FvM  

 - use an internal signal Qi and copy it to Q outside the edge sensitive condition?  can show me pls?

[Altera_Forum]

process(clk) begin if rising_edge(clk)then Qi <=(J and (not Qi)) or ((not K) and Qi); end if; qn <=not Qi ; Q <= Qi ; end process;

[Altera_Forum]

BTW, shouldn't  

qn <= not Qi; Q <= Qi  be outside the process?

[Altera_Forum]

--- Quote Start ---  BTW, shouldn't  qn <= not Qi; Q <= Qi  be outside the process?  --- Quote End ---   Yes, they must for correct simulation, or Qi needs to be added to the sensitive list.   Thanks!