Fmax for clksys (NIOSII in Cyclone Kit)

[Altera_Forum]

Hi, 

When I connect to NIOSII in Cyclone Kit 125MHz clksys from PLL, I can't load my processor program via IDE (appears hardware programmer window). How Fmax is correct? In Altera seminar 2004 materials for Cyclone and NIOSII/f is 125MHz...

[Altera_Forum]

Any number of things could be wrong. 

 1) Does your hardware design meet timing? 2) Are your memory connections correct? 3) Is your input clock driving 125MHz? 4) If you are using SDRAM, are you putting the correct phase shift on the clock? 5) (I should have asked this first) What board are you using (Nios Development Board or a Nios Eval Kit)?

[Altera_Forum]

i am a beginner  

how to put the correct phase shift on the clock? do i use pll?