I used multiple clks and multiple edges in one design.
Just wondering how does Quartus II calculate the Fmax for this case.
For example:
I have a critical path in clock of 400MHz, falling edge triggering: which I don't understand how Fmax is calculated.
Info: Fmax is 437.83MHz (period = 2.284ns)
Info: +Largest register to register requirement is 1.037ns
Info: +Setup relationship between source and destination is 1.250ns
Info: +Largest clock skew is 0.000ns
Info: -Micro clock to output delay of source is 0.109ns
Info: -Micro setup delay of destination is 0.104ns
Info: -Longest register to register delay is 0.929ns
Another path of 400MHz, rising edge triggering:
Fmax = 1/period = 1/(1.668+0.109+0.104)
Info: Fmax is 531.63MHz (period = 1.881ns)
Info: +Largest register to register requirement is 2.287ns
Info: +Setup relationship between source and destination is 2.500ns
Info: +Largest clock skew is 0.000ns
Info: -Micro clock to output delay of source is 0.109ns
Info: -Micro setup delay of destination is 0.104ns
Info: -Longest register to register delay is 1.668ns
Thanks,
