Quartus question

[Altera_Forum]

Quartus II gives this warning message: 

   Warning: Found 159 output pins without output pin load capacitance assignment     Warning: Pin "ENET_ADS_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis .... Q1) Does this cause any problems? Q2) Any idea what Quartus II settings can be used to fix this?  Thanks in advance

[Altera_Forum]

--- Quote Start ---   Quartus II gives this warning message:     Warning: Found 159 output pins without output pin load capacitance assignment     Warning: Pin "ENET_ADS_N" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis .... Q1) Does this cause any problems? Q2) Any idea what Quartus II settings can be used to fix this?  @Q2: - right click on the pin, which causes the warning  - locate   - locate in assignment editor  - check that <all> is enabled  - in an empty tab field under <assignment name> below location  double left click -> a window with a scrollbar should pop up  - scroll down to output pin load   - left click on this ^^^^^^ text, should get dark blue  - in the information window you can read the info about this property  - go to value: left click, enter a value you need  - exit this window, confirm to save changes  @Q1: until now I didn&#39;t take care of it. I just took the values suggested in the   samples. No problems with that.Some components seem to require this.  Might be someone knows an application note from altera how to   calculate /define this.    good luck.

[Altera_Forum]

--- Quote Start ---  originally posted by hootsmon@Apr 20 2006, 10:15 PM quartus ii gives this warning message:     warning: found 159 output pins without output pin load capacitance assignment     warning: pin "enet_ads_n" has no specified output pin load capacitance -- assuming default load capacitance of 0 pf for timing analysis .... q1) does this cause any problems? q2) any idea what quartus ii settings can be used to fix this?  thanks in advance <div align='right'><{post_snapback}> (index.php?act=findpost&pid=14534)</div>  --- Quote End ---    Output pin load capacitance assignment will effect timing simulation results. Based on my understanding, as long as you are not dealing with timing stringent design or board level design no necessary concern is needed.  For basic timing stringent design with small amount of pins, Quaruts II will automatically assign pins which are in similar logic level to the same I/O bank or adjacent I/O banks. Major timing issues can be studied without concerning capacitance.

[Altera_Forum]

Thanks :-)