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Hello everyone !
In my current baremetal project, I use a Cyclone V 5CSXFC6C6 and I want to use the HPS emac in RGMII. On the board I developped, i had to use the FPGA I/O to route the GMII signals of the HPS. My QSYS project is based on this project (for the emac management) : https://rocketboards.org/foswiki/projects/cyclonevrgmiiexampledesign So I use QSYS "Emac interface splitter" & "gmii to rgmii adapter" module to make the GMII to RGMII conversion. The PHY i use is the Mikrel KSZ9021RL. To initialize HPS Emac & PHY, I use the method described in Cyclone V Hard Processor System Technical Reference Manual (cv_5v4.pdf), Ethernet Media Access Controller / Ethernet MAC Programming model. The "EMAC FPGA interface initialization" seems to works fine in my HPS software :- I reset the PHY
- I reset the HPS EMAC0
- I configure the EMAC0_clk to 250MHz
- I bring the PHY out of reset and I check if rx_clk is present (it is the case)
- The Qsys "gmii-2-rgmii" adaptor that I developped is running, so I assume that the corresponding clocks are correctly propagating.
- I set the EMAC0 to GMII mode
- I start the Ethernet Controller FPGA interface
- I bring the EMAC out of reset
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