How to add an userlogic to the tri-state bridge?

[Altera_Forum]

I want add an user logic in CPLD to NiosII which resides in FPGA, the logic is some registers and I want to add it to the tri-state bridge, thus Nios can write or read these registers through the tri-state bridge address and data lines(the NiosII has SRAM and Flash outside, so add these registers to the tristate bridge would be convient and can also save some pins for FPGA).  

But how can I do it?

[Altera_Forum]

You can add using Interface to user logic. 

Write some hdl file and describe only ports. Data bus must be inout.  Open SOPC and run Interface to User logic, add file,  describe ports. In Instantiation tab choose Export Bus Ports. In timing tab set time.  After that correct your ptf file if it need.  For example:   SYSTEM_BUILDER_INFO   {  Bus_Type = "avalon_tristate";  Address_Alignment = "dynamic";  Address_Width = "4";  Data_Width = "8";  Has_IRQ = "0";  Has_Base_Address = "1";  Read_Wait_States = "160.0ns";  Write_Wait_States = "160.0ns";  Setup_Time = "40.0ns";  Hold_Time = "40.0ns";  Is_Memory_Device = "1";  Uses_Tri_State_Data_Bus = "1";  Is_Enabled = "1";  }  PORT_WIRING   {  PORT addr  {  width = "4";  direction = "input";  type = "address";  is_shared = "1";  }  PORT data  {  width = "8";  direction = "inout";  type = "data";  is_shared = "1";  }  PORT read_n  {  width = "1";  direction = "input";  type = "read_n";  }  PORT write_n  {  width = "1";  direction = "input";  type = "write_n";  }  }   You can use dynamic alignment (device_address[0] == avalon_address[0], data bus 8 bits) , and in program you could access to you port using structure # pragma pack(1) typedef struct _device {  unsigned short REG0; //All registers are 16 bits in this case  unsigned short REG1;   unsigned short REG2;  unsigned short REG3;  unsigned short REG4;  unsigned short REG5;  unsigned short REG6;  unsigned short REG7;  } device;# pragma pack()  device *p =(device*) DEVICE_BASE;   ....   p->REG0 = 0x00FF; ....

[Altera_Forum]

For example your device in CPLD 

 module yourdevice (reset, address, write, read, data); input reset; input write, read; inout [7:0] data; input [3:0] address;   reg [7:0] REG1; ....  assign data = (!address && read)? REG1:8&#39;bzzzzzzzz;  //some code always @ (address or reset or or write) begin  if (reset) REG1 <= 0;  else if (address==0) REG1 <= data; end  endmodule   Your hdl file for Interface to user logic:  module yourdevice ( reset, address, write, read, data); input reset; input write, read; inout [7:0] data; input [3:0] address;  endmodule

[Altera_Forum]

Thank you for your intensive explanation. 

I&#39;ll try it after a while. But, there may be an alternative as for the hdl interface file: if you do not specify a hdl file under the HDL FILES tab, add signals under the SIGNALS tab may also be ok.  I&#39;ll try them.  Thank you. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif

[Altera_Forum]

RemyMartin, 

 if you use &#39;Create New Component&#39; you will be guided in a message box. Add the signals you need and watch the message box for hints ( e.g. regarding input / output). Use e.g. &#39;new avalon tristate slave&#39; as interface for every signal, then go to submenue &#39;interface&#39;, enter a name, set timing parameters. Now go to &#39;Component Wizard&#39; and assign a new Component Name (instead of &#39;untiteled&#39;). After finishing you have a new component which can be added (as a copy). Editing this component later, does not change components already used. Due to faults the signals &#39;read&#39;, &#39;write&#39; and &#39;outputenable&#39; are never shared. You have to close SOPC-builder open the corresponding .ptf file and add <is_shared = "1"> to the pin settings. The signal &#39;irq_n&#39; will be ignored, &#39;irq&#39; can be used. The legacy component &#39;Interface To User Logic&#39; is easier to handle and functions well. Use Alteras &#39;mnl_avalon_bus.pdf&#39; for signal and timing reference.  hope this helps.  Mike

[Altera_Forum]

Thank you