From ftp://ftp.altera.com/up/pub/universi...am_ip_cores/90 (ftp://ftp.altera.com/up/pub/university_program_ip_cores/90) , I got a SRAM_Controller code to interface the SRAM to Avalon bus. It need 2 cycles for READ and 1 cycle for WRITE. Fro READ, it set up address and other control signal, and latch the data on the second cycle.
The SRAM on my board is -10. So if the system clock is 50MHz, there is no problem. However, if I increase sys clock to 100MHz, this code won't work. One cycel delay is needed between the address &control signals setup clock and data latch cycle, to get stable data on data bus.
I am a starter for FPGA and NIOS. Can anyone give suggestion on how to write RTL to add one cycle wait? Thanks.
