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so I need to create an echo(only one delay, not infinite) using DE1 board. the following is given code. It generate a delayed signal in a different channel in case 4.
I need to have a real echo signal. If you see "commented part" in case 4, it actually tried to add delayed signal to original to create an echo. but I guess it doesn't work(at least it doesn't sound like it)
I have a few concerns :
1. case statement 1 and 2 are taking 32 bits. why 8 bits for case 4? I tried with 16 and 32 bits, but it sounds like it's missing some data
2. can i literally just add an original signal of 32bits with a delayed signal of 32bits for output?.. or, should I shift or divide the delayed signal to reduce amplitude? and if I need to add the two signals, I guess I need a new 16 bit unsigned to store data?...OTL..
HELP ME, PLEASE~
#define Switches (volatile char *) SWITCH_PIO_BASE
#define LEDs (char *) LED_RED_BASE
#define max_width 8388608 // 8MBytes total, half will be used by left channel and half for right channel
#define max_width_by2 4194304 //4MBytes
#define delay 4000
int main()
{
//*note alt_u32 is an unsigned 32 bit integer defined in alt_types.h
alt_u32 length_read_l,length_read_r;
alt_u32 length_write_l,length_write_r;
alt_u32 sdram_addr_read_base_l = SDRAM_0_BASE; //base address of sdram
alt_u32 sdram_addr_read_top_limit_l = (SDRAM_0_BASE+max_width_by2-128); //sdram base + 4194304 - 128 , not sure why subtract 128
alt_u32 sdram_addr_read_base_r = SDRAM_0_BASE+max_width_by2; //sdram base + 4194304 2nd half of 8MB sdram, 1st half for left channel
alt_u32 sdram_addr_read_top_limit_r = (SDRAM_0_BASE+max_width_by2-128); //sdram base + 4194304 - 128
alt_u32 sdram_addr_read_counter_l=0;
alt_u32 sdram_addr_read_counter_r=0;
alt_u32 read_location_l=0;
alt_u32 read_location_r=0;
alt_u32 *read_address_l;
alt_u32 *read_address_r;
alt_u32 audiobuf_r[64];
alt_u32 audiobuf_l[64];
int switch_value,i;
int old_data,temp;
int x=0;
int y=0;
//clearing the audio buffers left and right
for (i=0;i<64;i++){
audiobuf_r[i] =0;
audiobuf_l[i]=0;
}
//reset the audio
alt_up_audio_reset_audio_core(); // resets the audio core by clearing the incoming and outgoing FIFOs
while (1)
{
switch_value=IORD(SWITCH_PIO_BASE,0); //the bits of the data register corresponds to the switches
switch(switch_value){
case 1:{ //left channel (case 1 corresponds to switch 0)
//write to write_fifo and read from read_fifo
read_location_l=sdram_addr_read_base_l+sdram_addr_ read_counter_l;//base address of sdram + offset (initially zero)
length_read_l=alt_up_audio_read_left_channel(&read _location_l, 32); //reading inputs from ADC via the fifo space and returning length
length_write_l=alt_up_audio_write_left_channel(&re ad_location_l, length_read_l ); //writing outputs to DAC via fifo space " "
alt_up_audio_write_right_channel(&audiobuf_r, length_read_l ); //writing dummy 0's outputs to DAC
//linear memory in to circular memory. Reads sdram from base to top address then resets to base
if (sdram_addr_read_counter_l<sdram_addr_read_top_lim it_l) //read counter initialized to zero,
{ sdram_addr_read_counter_l=sdram_addr_read_counter_ l+length_read_l;} //increment write counter by 32 bits of fifo space
else {sdram_addr_read_counter_l=sdram_addr_read_base_l; }// reset to the base address of sdram used for the left channel
break; //exits the case
}
case 2:{ //right channel (case 2 corresponds to switch 1)
//write to write_fifo of right channel and read from read_fifo
read_location_r=sdram_addr_read_base_r+sdram_addr_ read_counter_r;
length_read_r= alt_up_audio_read_right_channel(&read_location_r , 32); //reading inputs from ADC
length_write_r=alt_up_audio_write_right_channel(&r ead_location_r, length_read_r ); //writing outputs to DAC
alt_up_audio_write_left_channel(&audiobuf_l, length_read_r ); //writing dummy 0's outputs to DAC
//linear memory in to circular memory.
if (sdram_addr_read_counter_r<sdram_addr_read_top_lim it_r)
{ sdram_addr_read_counter_r=sdram_addr_read_counter_ r+length_read_r;} //increment write counter
else {sdram_addr_read_counter_r=sdram_addr_read_base_r; }
break;
}
case 4:{ //corresponds to switch 3
//write to write_fifo of left channel and read from read_fifo
read_address_l=sdram_addr_read_base_l+sdram_addr_r ead_counter_l; //base address of left channel plus offset
length_read_l= alt_up_audio_read_left_channel(read_address_l , 8); //reading inputs from ADC (incoming fifo) and store in read_address_l
length_write_l=alt_up_audio_write_left_channel(rea d_address_l, length_read_l); //writing outputs to DAC (outgoing fifo) from read_address_l
read_location_r=sdram_addr_read_base_r+sdram_addr_ read_counter_r; //current address in sdram to read
length_read_r= alt_up_audio_read_right_channel(read_address_l , 8); //reading inputs from ADC
x=x+8;
alt_up_audio_write_right_channel((read_address_l-delay), length_read_l ); //writing delayed values as outputs to DAC
//printf("x=%d length_read_r=%d read_l=%d read_r=%d \n",x,length_read_r,read_address_l,read_location_r );
/*
//PREVIOUSLY COMMENTED////// Partial code that was abandoned????
for(i=0;i<length_read_r;i++){
old_data=IORD((read_location_r+i-1000),0); //IORD defined in "altera_avalon_pio_regs.h"
//it reads data from read_location_r+i-1000 (previously stored data?)
audiobuf_r[i]=audiobuf_r[i]+old_data; // storing data in audiobuff_r until "length_read_r" (8 bits)
}
//alt_up_audio_reset_audio_core();
x=x+length_read_l; // 16 bits?
old_data=sdram_addr_read_base_r+y;//delay;
if(x>delay){
temp= alt_up_audio_write_right_channel(old_data, length_read_r ); //writing delayed values as outputs to DAC
y=y+temp;
}else
{alt_up_audio_write_right_channel(&audiobuf_r, length_read_r ); //writing delayed values as outputs to DAC
}
///////////////////////////
*/
//linear memory in to circular memory.
if (sdram_addr_read_counter_l<sdram_addr_read_top_lim it_l) //left headphone echo
{ sdram_addr_read_counter_l=sdram_addr_read_counter_ l+length_read_l;} //increment write counter
else {sdram_addr_read_counter_l=sdram_addr_read_base_l; }
/*
if (sdram_addr_read_counter_r<sdram_addr_read_top_lim it_r) //right headphone echo
{ sdram_addr_read_counter_r=sdram_addr_read_counter_ r+length_read_r;} //increment write counter
else {sdram_addr_read_counter_r=sdram_addr_read_base_r; } */
break;
}
default: //any other switch configuration
{
//left channel
//write to write_fifo of left channel and read from read_fifo
read_location_l=sdram_addr_read_base_l+sdram_addr_ read_counter_l;
length_read_l= alt_up_audio_read_left_channel(&read_location_l , 32); //reading inputs from ADC
length_write_l=alt_up_audio_write_left_channel(&re ad_location_l, length_read_l ); //writing outputs to DAC
//linear memory in to circular memory.
if (sdram_addr_read_counter_l<sdram_addr_read_top_lim it_l)
{ sdram_addr_read_counter_l=sdram_addr_read_counter_ l+length_read_l;} //increment write counter
else {sdram_addr_read_counter_l=sdram_addr_read_base_l; }
//right channel
//write to write_fifo of right channel and read from read_fifo
read_location_r=sdram_addr_read_base_r+sdram_addr_ read_counter_r;
length_read_r= alt_up_audio_read_right_channel(&read_location_r , 32); //reading inputs from ADC
length_write_r=alt_up_audio_write_right_channel(&r ead_location_r, length_read_r ); //writing outputs to DAC
//linear memory in to circular memory.
if (sdram_addr_read_counter_r<sdram_addr_read_top_lim it_r)
{ sdram_addr_read_counter_r=sdram_addr_read_counter_ r+length_read_r;} //increment write counter
else {sdram_addr_read_counter_r=sdram_addr_read_base_r; } } }}
return 0;}
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can someone give me an advice at least?

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